Asymmetric Chip Stack Structure for High Density Memory
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Solution Overview
Problem
Existing semiconductor packages face challenges in increasing memory capacity without increasing thickness, as stacking multiple chips leads to increased package thickness, which is undesirable.
Innovation Solution
The semiconductor package employs an asymmetric chip stack structure with offset chip stacks and spacers to create a stepwise sidewall configuration, allowing for increased chip density while maintaining a reduced overall package thickness, where the first chip stack's protrusion corner overlaps with the second chip stack's corner, and spacers of different thicknesses are used to adjust heights and reduce width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase memory capacity, then the memory capacity is improved, but the package thickness increases
Solution Approach 1:
The patent transitions from vertical stacking (single dimension) to a combination of vertical and lateral offset stacking (multiple dimensions). Chip stacks are arranged with lateral offsets and different heights, creating a three-dimensional configuration that increases chip density without proportionally increasing package thickness. The protrusion corners overlapping configuration optimizes space utilization in multiple dimensions simultaneously.
Solution Approach 2:
The patent implements nested chip stacks where smaller or shorter chip stacks are positioned within the lateral footprint of larger or taller chip stacks. This nesting arrangement allows multiple chips to occupy overlapping lateral spaces at different vertical levels, increasing memory capacity while maintaining a compact overall package thickness.
2Quantity of substance
If chip stacks are offset to increase chip density, then the chip density is improved, but the structural complexity increases
Solution Approach 1:
The patent employs asymmetric chip stack configurations where stacks have different lateral positions, different heights, and different numbers of chips. This asymmetry allows optimized space utilization and increased chip density while the regularity of the offset pattern maintains manufacturing feasibility. The asymmetric design is systematic rather than random, balancing complexity and density.
Solution Approach 2:
The patent divides the chip stack structure into multiple independent stack units, each with its own offset configuration. This segmentation allows each stack to be manufactured and positioned independently, simplifying the overall manufacturing process despite the complex final arrangement. The modular stack units can be systematically assembled to achieve the desired high-density configuration.
Data Source
AI summary
A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. The first protrusion corner of the first chip stack may protrude toward the second chip stack.