Asymmetric Circuit Board Structure for Low-Loss Semiconductor Packaging
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Solution Overview
Problem
High-performance computing systems face challenges in miniaturization and electrical performance due to limitations in packaging and assembling techniques, particularly in achieving lower transmission and insertion losses, while maintaining mechanical stability and thermal dissipation.
Innovation Solution
The use of a patterned conductive plate with ducts and a core dielectric layer, combined with a metallization layer and build-up stacks, enhances structural rigidity, thermal dissipation, and electrical performance by allowing asymmetric dielectric layer distribution and filled through-hole vias, which improves mechanical stability and reduces warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional packaging and assembling techniques are used, then manufacturing simplicity is maintained, but transmission loss and insertion loss increase
Solution Approach 1:
The circuit board is divided into multiple layers with distinct functions: a core layer containing the conductive plate and core dielectric layer, and build-up layers containing metallization layers and dielectric layers. This segmentation allows each layer to be optimized independently for electrical performance while maintaining manufacturing feasibility.
Solution Approach 2:
The circuit board employs asymmetric dielectric layer distribution where the core dielectric layer has different properties than the build-up dielectric layers. The core dielectric layer is positioned adjacent to the conductive plate while build-up dielectric layers are positioned away from it, creating asymmetric electrical characteristics that reduce transmission and insertion losses.
2Volume of moving object
If miniaturization is pursued, then device size is reduced, but mechanical stability and thermal dissipation deteriorate
Solution Approach 1:
The circuit board uses composite material structures combining conductive plates with dielectric layers. The conductive plate provides mechanical reinforcement and thermal dissipation pathways, while the dielectric layers provide electrical insulation. This composite structure enables miniaturization while maintaining mechanical stability and thermal performance.
Solution Approach 2:
The invention transitions from planar circuit board design to a multi-layer three-dimensional structure. Conductive plates are positioned within dielectric layers at different heights, creating vertical electrical pathways and improving thermal dissipation in the Z-direction while reducing the horizontal footprint of the device.
3Reliability
If conventional circuit board structures are used, then manufacturing cost is low, but electrical inductance and resistance properties are insufficient
Solution Approach 1:
The conductive plate and core dielectric layer are formed together in the core layer before the build-up layers are added. This preliminary formation of the core structure with optimized electrical properties allows subsequent build-up layers to be added without compromising the fundamental electrical characteristics, balancing manufacturing ease with electrical performance.
Data Source
AI summary
Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate. Bottommost conductive layer is disposed on bottommost dielectric layer and electrically connects to metallization layer. First build-up stack includes more conductive and dielectric layers than second build-up stack.