Asymmetric Conductive Lines for IC Mechanical Stability

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Solution Overview

Problem

The existing methods for forming electrically conductive lines in integrated circuits face issues with adhesion and mechanical stability, leading to potential separation and functionality failures due to mechanical stress and thermal expansion differences between materials.

Innovation Solution

The method involves forming a semiconductor structure with electrically conductive lines that have a first portion with a greater lateral dimension than a second portion, where the second portion is located at a greater distance from the lower conductive feature, enhancing mechanical stability by creating a rivet-like structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional methods are used to form electrically conductive lines with uniform cross-section, then the manufacturing process is simple, but the mechanical stability is poor leading to separation and functionality failures

Engineering Contradiction:
Improvemechanical stabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by forming electrically conductive lines with non-uniform cross-sectional areas. Specifically, the conductive lines have a larger cross-sectional area at certain regions (such as at interfaces with diffusion barrier layers or at connections between levels) and a smaller cross-sectional area in other regions. This asymmetric geometry provides mechanical anchoring that prevents separation while maintaining electrical conductivity, thereby improving reliability without requiring fundamentally new manufacturing processes.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent addresses mechanical stability by transitioning from a two-dimensional uniform cross-section to a three-dimensional varying cross-section. The conductive lines are formed with different widths or areas at different heights or positions along their length, creating a rivet-like structure that mechanically interlocks with surrounding materials. This dimensional variation provides mechanical stability while the deposition processes remain relatively conventional.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If materials with different thermal expansion coefficients are used in the conductive line structure, then the electrical performance can be optimized, but mechanical stress causes separation and failure

Engineering Contradiction:
Improveadhesion stabilityVSAvoidmechanical stress
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The patent applies parameter changes by varying the cross-sectional dimensions of the electrically conductive lines along their length. This geometric parameter variation creates mechanical interlocking features that increase adhesion strength. The larger cross-sectional areas at critical interfaces provide enhanced mechanical anchoring that compensates for the mechanical stress generated by thermal expansion differences between materials, thereby improving adhesion stability.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements beforehand cushioning by designing the conductive lines with enlarged cross-sectional areas at positions where mechanical stress is expected to be highest, such as at interfaces with diffusion barrier layers or where connections between different levels occur. These geometric features act as mechanical cushions or stress distributors that prevent separation before it can occur during thermal cycling or mechanical loading.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS7622391B2Method of forming an electrically conductive line in an integrated circuit
Publication Date: 2009.11.24 ADVANCED MICRO DEVICES INC
  • US7622391B2 patent drawing
  • US7622391B2 patent drawing
  • US7622391B2 patent drawing

AI summary

A method of forming a semiconductor structure comprises providing a semiconductor structure comprising a layer of a dielectric material provided over an electrically conductive feature. An opening is formed in the layer of dielectric material. The opening is located over the electrically conductive feature and has a first lateral dimension. A cavity is formed in the electrically conductive feature. The cavity has a second lateral dimension being greater than the first lateral dimension. The cavity and the opening are filled with an electrically conductive material.