Asymmetric Contact Layout for Transistor Strain and Capacitance
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Solution Overview
Problem
Conventional strategies face challenges in simultaneously achieving low contact resistance and minimizing adverse effects on transistor characteristics, such as strain and fringing capacitance, in highly scaled field effect transistors.
Innovation Solution
The layout of contact structures in semiconductor devices is locally varied to balance low ohmic contact requirements with strain-inducing mechanisms and fringing capacitance, with asymmetric designs for drain and source contacts to optimize transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact structures are made larger to reduce contact resistance, then contact resistance decreases, but fringing capacitance increases and strain-inducing mechanisms are compromised
Solution Approach 1:
The patent applies different lateral target dimensions to different contact structures based on their specific location and function. Source contacts have one dimension while drain contacts have another dimension, optimizing each contact's performance characteristics locally rather than using a uniform size for all contacts
Solution Approach 2:
The patent introduces asymmetry in the contact structure design by making drain contacts and source contacts have different lateral target dimensions. This asymmetric design allows optimization of the drain contact for low resistance while the source contact is optimized for reduced fringing capacitance, resolving the contradiction between these two requirements
2Ease of manufacture
If conventional uniform contact layouts are used, then manufacturing is simplified, but transistor performance is compromised due to increased fringing capacitance and contact resistance
Solution Approach 1:
The patent transitions from uniform contact layouts to locally optimized contact layouts where each contact structure has specific lateral target dimensions tailored to its location. This allows manufacturing to remain relatively simple while significantly improving transistor performance by reducing fringing capacitance and contact resistance through localized optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by reducing contact resistance and fringing capacitance, thereby improving switching characteristics and current drive capability while maintaining desired series resistance.
Implementation Method 1
the intrinsic stress may be transferred into the underlying semiconductor material so as to finally obtain a respective strain in the channel region
Implementation Method 2
well-approved materials, such as silicon dioxide, silicon nitride, carbon enriched silicon nitride and the like, may be formed by plasma enhanced chemical vapor deposition (PECVD) techniques
Data Source
AI summary
By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.