Asymmetric Control Paths for Storage Read Latency
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Solution Overview
Problem
Multi-chip storage devices face latency and sampling window limitations due to size and layout constraints, which hinder increased read speeds.
Innovation Solution
The implementation of a circuit configuration with varying control and clock path lengths for memory banks, where the second bank is closer to the control interface and has a longer control path, and the first bank has a longer data path, sharing a common data bus, to optimize data transfer and minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred from memory cells to controller via external data bus, then data can be read, but latency and sampling window limitations occur due to size and layout constraints
Solution Approach 1:
The patent applies local quality by making control paths asymmetric - the second bank (closer to control interface) receives control signals earlier than the first bank (farther from control interface). This compensates for the longer data path length from the second bank to the data receiving circuit, ensuring both banks can output data at the same time despite different physical distances.
Solution Approach 2:
The patent implements preliminary action by advancing the control signal transmission to the second bank before the first bank. The control interface sends control signals to the second bank earlier, allowing it to prepare its data for output in advance, so that both banks' data arrives simultaneously at the data receiving circuit despite the second bank's longer data path.
2Loss of time
If control paths are made equal length, then signal timing is simplified, but banks at different physical positions cannot compensate for propagation delays
Solution Approach 1:
The patent directly applies asymmetry by intentionally making control paths of different lengths for different banks. The second bank (physically closer to control interface) is given a longer control path delay, while the first bank (physically farther) receives control signals earlier. This asymmetric configuration compensates for the asymmetric physical positions and data path lengths, enabling synchronized data output from all banks.
3Duration of action of moving object
If sampling windows are increased, then more data can be captured, but layout constraints prevent window expansion
Solution Approach 1:
The patent applies dynamics by making the control signal transmission timing adjustable and adaptive for each bank based on its physical position. The control interface dynamically adjusts when to send control signals to each bank - earlier for farther banks and later for closer banks - allowing the system to optimize sampling windows without changing the physical chip layout.
Data Source
AI summary
A system may include a controller, a data receiving circuit, and a plurality of banks. The banks may send data to the data receiving circuit via a common data bus. The controller may control the communication of the data to the receiving circuit by sending control signals and clock signals to the banks. Relative lengths of control signal paths and clock signal paths may be directly related to each other and inversely related to relative lengths of data paths.