Asymmetric Processor Core Cooperation for Interrupt Handling
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Solution Overview
Problem
High-function processor cores experience significant inefficiencies due to hardware interrupts and exceptions, which disrupt the flow of instruction execution and require complex architectures to manage, leading to inefficiencies in handling interrupts and exceptions.
Innovation Solution
A processor component with a higher function core and a lower power core that cooperate to minimize the impact of interrupts, where the lower power core handles time-sensitive tasks and signals the higher function core for less time-sensitive tasks, allowing for dynamic mode switching between cores based on processing demand.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a higher function core uses complex architecture features (deep pipeline, large caches, sophisticated prefetch and branch prediction), then instruction execution performance is improved, but the core becomes more vulnerable to and inefficient at handling hardware interrupts and exceptions
Solution Approach 1:
The processor is divided into two separate cores: a higher function core optimized for instruction execution with complex features (deep pipeline, large caches, sophisticated prefetch and branch prediction) and a lower power core optimized for handling interrupts and exceptions. This segmentation allows each core to be specialized for its specific function, resolving the contradiction between execution performance and interrupt handling efficiency.
Solution Approach 2:
The lower power core acts as an intermediary between hardware interrupts and the higher function core. It receives interrupts and exceptions from hardware components and handles them, then signals the higher function core when attention is needed. This intermediary approach protects the complex higher function core from direct interrupt handling while maintaining system responsiveness.
2Device complexity
If a single core handles both high-performance instruction execution and interrupt handling, then device complexity is reduced, but processing efficiency deteriorates due to context switching and pipeline flushes
Solution Approach 1:
The processor architecture is segmented into two cores with distinct responsibilities: the higher function core for instruction execution and the lower power core for interrupt handling. This segmentation improves processing efficiency by eliminating context switching and pipeline flushes that would occur in a single-core design, while the modular architecture keeps device complexity manageable.
Solution Approach 2:
The invention merges the functions of instruction execution and interrupt handling into separate cores within a single processor package. The lower power core is coupled to the higher function core through inter-core communication interfaces, allowing efficient coordination while maintaining architectural simplicity at the system level.
3Loss of time
If the higher function core continuously monitors and handles all interrupts, then response time is improved, but power consumption increases
Solution Approach 1:
The processor is segmented into a higher function core and a lower power core with different operational characteristics. The lower power core handles time-sensitive interrupt response while the higher function core handles less time-sensitive tasks, allowing each core to operate at appropriate power levels and reducing overall power consumption while maintaining fast interrupt response.
Solution Approach 2:
The lower power core handles only the essential interrupt handling functions rather than all processing tasks. This partial action approach allows fast interrupt response for critical tasks while the higher function core can be in lower-power states for less critical processing, optimizing the balance between response time and power consumption.
Data Source
AI summary
Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.