Asymmetric Cored IC Package Supports for Reduced Z-Height
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Solution Overview
Problem
Conventional integrated circuit (IC) packages face challenges in miniaturization due to constraints on size, power consumption, noise levels, manufacturability, and high-frequency operation, with symmetric cored substrates leading to underutilization of buildup layers and inadequate power delivery for future devices.
Innovation Solution
The development of asymmetric cored IC package supports with different numbers of buildup layers on each face of the core, allowing for optimized pathway density and integration of inductors with improved inductance and Q values, enabling reduced z-height and enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If symmetric cored substrates are used, then manufacturing is simplified, but buildup layers are underutilized and z-height increases
Solution Approach 1:
The patent applies asymmetry by configuring different numbers of buildup layers on opposite faces of the cored substrate. The first face has a first number of buildup layers while the second face has a second number of buildup layers, where these numbers are intentionally different. This asymmetric configuration optimizes pathway density distribution and reduces overall z-height while maintaining manufacturing feasibility through standardized layering processes.
Solution Approach 2:
The patent implements local quality by tailoring the number of buildup layers to the specific pathway density requirements of each face. The first buildup region is configured with more layers where higher pathway density is needed, while the second buildup region has fewer layers where lower density suffices. This localized optimization ensures each region has the appropriate structural characteristics for its functional requirements.
2Power
If more buildup layers are added to increase pathway density, then power delivery improves, but z-height and package volume increase
Solution Approach 1:
The asymmetric configuration allows concentrated pathway density and power delivery capability in the first buildup region with more layers, while the second buildup region uses fewer layers. This distributes the power delivery function efficiently across the structure, achieving adequate power supply without uniformly increasing z-height across the entire substrate.
Solution Approach 2:
The patent optimizes power delivery by utilizing the lateral dimension through asymmetric layer distribution rather than uniformly increasing vertical height. By concentrating buildup layers on specific faces where pathway density is critical, the design achieves improved power delivery capability while controlling overall package volume through strategic dimensional allocation.
3Reliability
If inductors are integrated into the core region, then electrical performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges the inductor structure with the cored substrate by integrating inductors directly into the core region. The inductors share the same structural framework and manufacturing process steps as the substrate itself, combining multiple functions into a unified structure. This integration approach improves electrical performance by reducing parasitic effects while avoiding the need for separate inductor assembly processes.
Data Source
AI summary
Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.