Asymmetric Cyclic Deposition Etch for Source Drain Resistivity
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Solution Overview
Problem
Existing methods for forming source and drain regions in semiconductor devices, such as CMOS transistors, face challenges in achieving low resistivity and sufficient carbon concentration while maintaining high throughput due to limitations in etching rates and dopant activation levels, particularly at advanced technology nodes.
Innovation Solution
The implementation of an asymmetric cyclic deposition and etch (ACDE) process using Cl2 as an etchant, which differs from traditional methods by incorporating a preparation layer of carbon-doped silicon and subsequent phosphorus soaking to enhance epitaxial growth, allowing for higher dopant incorporation and reduced etching time, thereby achieving lower resistivity and sufficient carbon concentration in the silicon-containing material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional etching methods are used, then etching process is simpler, but etching rate is lower and etching time is longer
Solution Approach 1:
The etching process is divided into multiple cyclic steps including deposition of silicon-containing material, etching with Cl2, and conditional repetition based on thickness measurements. This segmentation enables precise control of etching rate and depth while maintaining process simplicity through automation.
Solution Approach 2:
The patent implements periodic cyclic deposition and etching actions where silicon-containing material is deposited and then etched in repeating cycles. This periodic action achieves high etching rates while maintaining precision through the rhythmic alternation of deposition and removal phases.
2Reliability
If higher dopant concentration is achieved, then resistivity decreases, but carbon concentration control becomes more difficult
Solution Approach 1:
The patent employs feedback control by measuring the thickness of the silicon-containing material layer after each cycle and comparing it to a target thickness. The process automatically adjusts by repeating or terminating cycles based on this feedback, ensuring precise carbon concentration control while achieving desired dopant levels and low resistivity.
Solution Approach 2:
The patent changes process parameters including Cl2 flow rate, deposition temperature, and cycle repetition based on real-time thickness measurements. These parameter adjustments enable simultaneous optimization of dopant incorporation and carbon concentration uniformity, achieving low resistivity with precise compositional control.
3Quantity of substance
If epitaxial growth is enhanced, then dopant incorporation increases, but process time increases
Solution Approach 1:
The patent maintains continuous useful action by performing deposition and etching in tight cyclic sequences without significant idle time. This continuous process enhances dopant incorporation efficiency while minimizing total process time, as each cycle immediately follows the previous one with automated transitions.
Solution Approach 2:
The patent applies partial etching actions where only portions of the deposited material are removed in each cycle, allowing dopant incorporation to occur during deposition while limiting time-consuming etching to what is necessary for thickness control. This partial action approach optimizes the balance between dopant incorporation and process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in source and drain regions with lower resistivity and higher carbon concentration, meeting the demands of advanced technology nodes by improving throughput and maintaining process control, while ensuring sufficient dopant activation and uniformity.
Implementation Method 1
depositing an epitaxial silicon-containing layer in the recesses, wherein the depositing of the epitaxial silicon-containing layer uses an asymmetric cyclic deposition and etching (ACDE) process
Implementation Method 2
depositing an epitaxial silicon-containing layer in the recesses, wherein the depositing of the epitaxial silicon-containing layer uses an asymmetric cyclic deposition and etching (ACDE) process
Implementation Method 3
The ACDE process uses Cl2 an etchant
Implementation Method 4
incorporating a preparation layer of carbon-doped silicon and subsequent phosphorus soaking to enhance epitaxial growth, allowing for higher dopant incorporation
Implementation Method 5
incorporating a preparation layer of carbon-doped silicon and subsequent phosphorus soaking to enhance epitaxial growth, allowing for higher dopant incorporation
Data Source
AI summary
The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described uses Cl2 as an etchant during the epitaxial formation of the S/D regions. The mechanisms involve using an asymmetric cyclic deposition and etch (ACDE) process that forms a preparation layer enable epitaxial growth of the following epitaxial layer with transistor dopants. The mechanisms also involve soaking the surface of substrate with dopant-containing precursors to enable sufficient incorporation of transistor dopants during the epitaxial growth of the S/D regions. By using Cl2 as etchants, the mechanisms also enables high throughput of the epitaxial growth of the S/D regions.