Asymmetric Data Communication Bus Lane Allocation
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Solution Overview
Problem
Current interconnect standards, such as PCI-e, allocate symmetric bus lanes for host-to-device and device-to-host communications, leading to inefficiencies due to asymmetrical data bandwidth requirements in systems like machine learning accelerators and neural network processors, where ingress data bandwidth often exceeds egress by several times.
Innovation Solution
A software control loop dynamically configures asymmetric links by identifying hardware devices, generating a system topology, and allocating different numbers of bus lanes based on asymmetric bandwidth requirements, allowing for dynamic reconfiguration of bus lanes as ingress or egress lanes based on data transfer patterns and predictive analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If symmetric bus lane allocation is used in current interconnect standards, then device complexity and ease of manufacture are maintained, but communication efficiency deteriorates due to asymmetrical data bandwidth requirements
Solution Approach 1:
The patent implements dynamic bus lane allocation where the host processor can reconfigure the number of lanes allocated to each device based on real-time bandwidth requirements. The system transitions from static symmetric allocation to dynamic asymmetric allocation, allowing bus lanes to be adjusted during operation to match actual data transfer needs of different devices.
Solution Approach 2:
The patent changes the parameter of bus lane allocation from fixed symmetric values to variable asymmetric values. The host processor modifies allocation parameters based on measured or predicted bandwidth requirements, enabling the system to adapt lane configuration to match the asymmetrical data transfer patterns of devices like machine learning accelerators.
2Reliability
If excess bus lanes are allocated to accommodate peak asymmetric bandwidth requirements, then bandwidth capacity is sufficient, but resource utilization deteriorates due to underutilization during low-demand periods
Solution Approach 1:
The system dynamically adjusts bus lane allocation based on actual bandwidth requirements rather than allocating excess capacity for peak demands. The host processor monitors or predicts bandwidth needs and reconfigures lane allocation accordingly, ensuring sufficient capacity during high-demand periods while minimizing resource usage during low-demand periods.
Solution Approach 2:
The patent changes the allocation parameters from fixed over-provisioning to variable on-demand allocation. By modifying the number of active bus lanes based on real-time or predicted workload characteristics, the system maintains reliable bandwidth capacity when needed while avoiding the energy waste of maintaining excess capacity during low-utilization periods.
3Productivity
If asymmetric bus lane allocation is implemented, then communication efficiency improves by matching actual traffic patterns, but device complexity increases due to dynamic reconfiguration requirements
Solution Approach 1:
The host processor serves multiple functions: it acts as the central control unit for bus lane allocation, the data processing unit, and the decision-making entity for bandwidth management. By consolidating these functions in the existing host processor rather than adding dedicated control hardware, the system achieves asymmetric allocation without proportionally increasing overall device complexity.
Solution Approach 2:
The system implements feedback mechanisms where the host processor monitors actual data transfer patterns and uses this information to adjust bus lane allocation. The feedback loop enables the system to learn from actual workload characteristics and optimize lane allocation accordingly, improving efficiency while keeping the control logic software-based and flexible.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.