Asymmetric Diffusion Barrier in Vertical Memory Cell Interconnects
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Solution Overview
Problem
Vertical memory cell strings in flash memory face challenges due to increased vertical thickness and diffusion issues of conductivity-doping material, which can adversely impact programmable memory cells, especially in the outermost portions of the lower stack.
Innovation Solution
An elevationally-extending string of memory cells is formed with an upper stack and a lower stack, each comprising vertically-alternating tiers of control gate material and insulating material, with a conductive interconnect using conductively-doped semiconductor material that includes an asymmetric diffusion barrier to allow greater dopant diffusion into the upper stack channel pillar than the lower stack pillar, ensuring effective programmable charge storage transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical memory cell strings are used to reduce horizontal area, then the horizontal area occupied by memory cells is reduced, but the vertical thickness increases and dopant diffusion issues adversely impact programmable memory cells
Solution Approach 1:
The patent applies local quality by creating an asymmetric diffusion barrier structure where the lower portion of the conductive interconnect has different dopant concentration characteristics compared to the upper portion. Specifically, the lower portion has reduced dopant concentration or enhanced barrier properties to prevent unwanted diffusion into the lower stack channel, while the upper portion maintains normal conductivity for proper operation of upper stack memory cells.
Solution Approach 2:
The patent implements asymmetry through the conductive interconnect structure that has non-uniform dopant distribution along its vertical extent. The asymmetric diffusion barrier creates different diffusion characteristics in the upward versus downward directions, allowing selective control of dopant movement to protect the lower stack while maintaining functionality of the upper stack.
2Reliability
If conductively-doped polysilicon is used for conductive interconnect, then electrical coupling between channel pillars is achieved, but dopant diffusion adversely impacts programmable memory cells in the outermost portion of the lower stack
Solution Approach 1:
The conductive interconnect is designed with spatially varying dopant concentration, where the lower portion has modified dopant characteristics (reduced concentration or different profile) compared to the upper portion. This local quality variation allows the interconnect to maintain electrical conductivity while creating a diffusion barrier at the critical interface with the lower stack channel.
Solution Approach 2:
The asymmetric diffusion barrier acts as an intermediary layer within the conductive interconnect that mediates between the need for electrical conductivity and the need to prevent dopant diffusion. This intermediate structure with its unique dopant profile serves as a buffer zone that controls the interaction between the conductive interconnect and the lower stack channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the horizontal area occupied by memory cells while maintaining efficient programmability and reducing dopant diffusion issues, enhancing the performance and reliability of memory cells.
Implementation Method 1
Some of the conductivity-producing dopant is thermally diffused elevationally out of the conductively-doped semiconductor material. An asymmetric diffusion barrier is used during the thermally diffusing to thermally diffuse more of said dopant upwardly into the upper stack channel pillar than diffusion of said dopant, if any, into the lower stack channel pillar.
Data Source
AI summary
An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.