Asymmetric Display Panel Driving with Boosting Clock Signal
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Solution Overview
Problem
Asymmetric display panels require efficient methods to drive gate lines disconnected from the display area without compromising the image inversion process, as existing solutions often lead to inefficient use of gate driver integrated circuits.
Innovation Solution
A method involving a boosting clock signal during the blanking period and a gate clock signal during the display period, managed by a microcontroller and multiplexer, to drive gate lines disconnected and connected to the display area respectively, enabling image inversion on asymmetric display panels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate driver integrated circuits are used to drive display panel gate lines, then the display panel can be driven, but some gate lines remain disconnected from the display area causing inefficient utilization
Solution Approach 1:
The patent applies dynamics by making the clock signal configurable - switching between a first clock signal for normal operation and a second clock signal with different frequency or duty cycle for image inversion mode. This dynamic adjustment allows the same gate driver integrated circuit to efficiently handle both connected and disconnected gate lines under different operating conditions, improving utilization without adding hardware complexity
Solution Approach 2:
The patent changes the clock signal parameters (frequency, duty cycle) based on operating mode. By providing a second clock signal with different characteristics than the first clock signal, the system optimizes the driving waveform for disconnected gate lines during image inversion, thereby improving gate driver utilization efficiency without requiring additional circuits
2Adaptability or versatility
If image inversion is implemented on asymmetric display panel, then display flexibility is improved, but the disconnected gate lines cause inversion errors
Solution Approach 1:
The patent introduces a clock generator as an intermediary component that produces different clock signals for different operating modes. This intermediary enables the system to switch between normal operation and image inversion modes, allowing the disconnected gate lines to be properly handled during inversion through the second clock signal, thus maintaining both flexibility and reliability
Solution Approach 2:
The patent uses periodic clock signals with different characteristics for different phases of operation. The first clock signal operates during normal display mode while the second clock signal operates during image inversion mode, providing the necessary periodic driving action for disconnected gate lines to achieve accurate inversion without compromising reliability
3Device complexity
If existing gate driver circuits are used without modification, then device simplicity is maintained, but image inversion process fails on asymmetric panels
Solution Approach 1:
The patent makes the existing gate driver integrated circuit multi-functional by providing it with two different clock signals. The same circuit handles both normal operation (using first clock signal) and image inversion (using second clock signal), eliminating the need for separate inversion circuits while maintaining full adaptability including image inversion capability on asymmetric panels
Data Source
AI summary
An asymmetric display panel has driver integrated circuits. When the asymmetric display panel is in an image inversion state, a boosting clock signal is transmitted to drive the data lines or the scan lines that are disconnected from the asymmetric display panel. A pulse number of the boosting clock signal is equal to a number of the data lines or scan lines that are disconnected from the asymmetric display panel.