Asymmetric Display Transistor Layout for Higher Circuit Density
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Solution Overview
Problem
Current display devices face challenges in increasing the layout density of elements and circuits to meet higher resolution requirements.
Innovation Solution
The display device incorporates a substrate with a peripheral region containing transistors with non-linearly symmetrical electrodes and signal lines arranged between them, allowing for a more compact design by optimizing the width and arrangement of the electrodes and signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If element and circuit layout density is increased to meet higher resolution requirements, then display resolution is improved, but circuit design complexity increases
Solution Approach 1:
The patent applies asymmetry by designing the first electrode with a first width and the second electrode with a second width that is different from the first width. This asymmetric electrode configuration optimizes the transistor layout, allowing for reduced transistor area while maintaining electrical performance, thereby enabling higher circuit layout density to achieve higher display resolution
Solution Approach 2:
The patent implements local quality by varying the width of electrodes at different locations within the transistor structure. The first electrode has a different width compared to the second electrode, allowing each region to be optimized for its specific function - this localized differentiation enables more efficient space utilization and reduces overall transistor footprint while maintaining the required electrical characteristics for high-resolution displays
Data Source
AI summary
A display device including a substrate and a circuit is provided. The substrate has a peripheral region. The circuit is disposed on the peripheral region and includes a plurality of transistors. One of the plurality of transistors includes a semiconductor layer, a first electrode, and a second electrode. The semiconductor layer includes a channel region. The first electrode is disposed at a side of the channel region and includes a first portion. The second electrode is disposed at another side of the channel region and includes a second portion. In a horizontal direction, a width of the first portion of the first electrode is greater than a width of the second portion of the second electrode.