Asymmetric Doherty Power Amplifier for Backed-Off Linearity
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Solution Overview
Problem
Doherty power amplifiers face inefficiencies at lower power levels and are susceptible to linearity degradation due to load variations in RF communication systems, particularly in advanced modulation schemes like 5G waveforms with high peak-to-average ratio (PAPR) and non-centered output power.
Innovation Solution
Implementing an asymmetric Doherty power amplifier configuration with a peaking amplifier having a smaller output transistor array size compared to the carrier amplifier, which provides a sharper amplitude distortion response with minimal phase distortion, improving adjacent channel leakage ratio (ACLR) and linearity at backed-off power levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional symmetric Doherty power amplifier is used, then the amplifier can operate at high power levels, but it suffers from inefficiencies at lower power levels and linearity degradation due to load variations
Solution Approach 1:
The patent applies asymmetry by configuring the peaking amplifier with a smaller output transistor array size than the carrier amplifier. This asymmetric configuration allows the peaking amplifier to activate at lower power levels with sharper amplitude distortion response, improving efficiency and linearity in the lower power operating range while maintaining high power capability through the carrier amplifier.
2Device complexity
If the peaking amplifier has the same size as the carrier amplifier, then the amplifier design is symmetric and simple, but it causes amplitude distortion and linearity degradation at backed-off power levels
Solution Approach 1:
The patent deliberately introduces asymmetry in the amplifier configuration by making the peaking amplifier's output transistor array smaller than the carrier amplifier's. This asymmetric design provides sharper amplitude distortion response at backed-off power levels, improving linearity and reducing adjacent channel leakage ratio while maintaining acceptable design complexity.
3Adaptability or versatility
If advanced modulation schemes with high PAPR are used, then data transmission capability is improved, but the amplifier becomes more susceptible to linearity degradation and maximum power reduction
Solution Approach 1:
The asymmetric Doherty configuration with smaller peaking amplifier transistor array provides sharper amplitude distortion response that better handles the high peak-to-average power ratio signals from advanced modulation schemes. This improves linearity and reduces maximum power reduction while maintaining support for high-order modulations.
Solution Approach 2:
The patent applies local quality by optimizing the peaking amplifier's transistor array size specifically for handling peak power events in high PAPR signals. The smaller peaking amplifier is designed to activate during peak conditions, providing localized improvement in linearity and amplitude distortion where it is most needed for advanced modulation schemes.
Data Source
AI summary
Asymmetric Doherty power amplifiers are disclosed. In certain embodiments, a Doherty power amplifier includes a carrier amplifier that generates a radio frequency carrier signal based on amplifying a radio frequency input signal, a peaking amplifier that generates a radio frequency peaking signal based on amplifying the radio frequency input signal, and a phase shifting and combining circuit configured to combine the radio frequency carrier signal and the radio frequency peaking signal to generate a radio frequency output signal. The carrier amplifier and the peaking amplifier have asymmetric amplifier sizes.