DRAM Memory Layout with Asymmetric Active Areas and Self-Aligned Node Contacts
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Solution Overview
Problem
Conventional memory cell layouts face challenges in achieving high integration and small cell size due to limitations in design, particularly in dynamic random access memory (DRAM) layouts where word lines are perpendicular to bit lines, leading to inefficiencies in area utilization.
Innovation Solution
The proposed memory layout structure features an active area array with recessed gate structures, self-aligned node contact plugs, and a unique arrangement of word and bit lines that cross over each other, allowing for a smaller repeating unit area of 6 F2 or 4 F2 by optimizing the placement and connection of diffusion regions, word lines, and bit lines, enabling a self-alignment process for improved contact efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional DRAM layout with perpendicular word lines and bit lines is used, then the layout is simple to manufacture, but the cell area is large (8 F2)
Solution Approach 1:
The patent applies asymmetry by arranging active areas at non-perpendicular angles (e.g., 45 degrees) relative to word lines, breaking the conventional symmetric perpendicular arrangement. This asymmetric layout enables more efficient space utilization, reducing the repeating unit area from 8 F2 to 6 F2 or 4 F2 while maintaining manufacturability through self-aligned processes.
Solution Approach 2:
The patent utilizes self-aligned node contact plugs that extend vertically between adjacent word lines and bit lines, adding a vertical dimension to the contact structure. This three-dimensional approach allows node contacts to be positioned precisely at the intersection of word and bit lines without requiring additional lateral space, thereby reducing the overall cell footprint.
2Quantity of substance
If active areas are arranged in parallel rows perpendicular to word lines, then the manufacturing process is straightforward, but the integration density is limited
Solution Approach 1:
The patent employs asymmetric angular arrangement of active areas (e.g., 45-degree angle) relative to word lines, enabling higher integration density by optimizing the geometric packing of memory cells. This asymmetric configuration allows more active areas to be packed into the same area while maintaining alignment with the self-aligned fabrication process, achieving 6 F2 or 4 F2 repeating units.
Solution Approach 2:
The patent implements self-aligned node contact plugs that automatically position themselves at the intersections of word lines and bit lines through the fabrication process itself. This self-alignment mechanism eliminates the need for complex additional alignment steps, maintaining manufacturing ease while enabling higher integration density through optimized active area arrangements.
3Reliability
If bit line contact plugs are located between two memory cells, then the bit line can engage two memory cells, but the contact area is limited
Solution Approach 1:
The patent transitions from planar contact structures to three-dimensional self-aligned node contact plugs that extend vertically between adjacent word lines and bit lines. This vertical extension increases the contact area and improves contact reliability by establishing multiple contact points, while the self-aligned fabrication process ensures precise positioning without requiring additional lateral space.
Data Source
AI summary
A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.