Asymmetric DRAM Cell with Columnar Capacitor
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Solution Overview
Problem
Conventional DRAM cell structures face challenges with short channel effects as the access transistor's length decreases, leading to increased off-current and decreased on-current, which negatively impact retention time and access time.
Innovation Solution
A DRAM cell structure is designed with a columnar capacitor and an asymmetric access transistor, where a semiconductor fin and column are doped with opposite conductivity type dopants, forming an inner electrode, and a dielectric and conductive layer are used to create an outer electrode and gate electrode, reducing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the length of the access transistor is decreased to achieve higher density, then the device size is reduced, but the short channel effect increases causing increased off-current and decreased on-current
Solution Approach 1:
The patent applies asymmetry by creating an asymmetric transistor structure where the channel width varies along the channel length. Specifically, the channel width is wider at the source end and narrower at the drain end, which helps suppress short channel effects while maintaining small device footprint. This asymmetric geometry modifies the electric field distribution to reduce off-current without sacrificing on-current
Solution Approach 2:
The patent implements local quality by introducing a halo implantation region that is localized at specific positions within the transistor structure. The halo region has different doping characteristics than the bulk channel, creating localized modifications to the electric field and carrier distribution. This local quality change helps control short channel effects without affecting the entire device structure
2Productivity
If the access transistor length is decreased for scaling, then the density increases, but the retention time deteriorates due to increased off-current
Solution Approach 1:
The asymmetric channel width profile (wider at source, narrower at drain) reduces the off-current by modifying the subthreshold slope and reducing leakage paths. This allows the transistor to maintain better charge retention in the capacitor even at scaled dimensions, thereby improving retention time while maintaining high density
Solution Approach 2:
The halo implantation is performed as a preliminary doping step before source and drain formation. This preliminary action creates a pre-configured doping profile that anticipates and compensates for short channel effects before the transistor is fully formed, ensuring better retention characteristics from the outset
3Area of stationary object
If the access transistor length is decreased for scaling, then the device area is reduced, but the access time deteriorates due to decreased on-current
Solution Approach 1:
The asymmetric channel design with wider width at the source end increases the on-current by providing a larger cross-sectional area for carrier flow at the injection point. This compensates for the reduced channel length effect, maintaining fast access times despite the smaller overall device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces short channel effects, improving the retention time and access time of the DRAM cell by optimizing the doping and structure of the access transistor and capacitor.
Implementation Method 1
The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type
Implementation Method 2
A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column
Implementation Method 3
The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode
Data Source
AI summary
A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.