DRAM Interleaving for Asymmetric Ranks and Refresh Power
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Solution Overview
Problem
Current DRAM rank interleaving schemes do not effectively increase DRAM usage efficiency for systems with asymmetric size DRAM ranks, and they incur costly overhead for partial array self-refresh and partial array auto-refresh due to unused interleaving blocks.
Innovation Solution
The method involves portion interleaving for asymmetric size DRAM ranks, which includes determining an asymmetric memory portion assignment, calculating a consumed address space offset, modifying addresses of interleave units, and assigning these units to interleave granules in a compact manner to optimize memory usage and reduce refresh power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current DRAM rank interleaving schemes are used, then DRAM usage efficiency is improved for symmetric ranks, but DRAM usage efficiency is not improved for asymmetric size ranks
Solution Approach 1:
The patent applies asymmetry by implementing different interleave unit sizes for different DRAM ranks based on their capacity. Instead of forcing symmetric interleaving, the system calculates and assigns interleave units proportionally to each rank's size, allowing asymmetric ranks to be efficiently utilized while maintaining the benefits of interleaving for all ranks.
Solution Approach 2:
The patent changes the parameter of interleave unit size dynamically based on rank capacity. By calculating the interleave unit size as a function of rank size (e.g., interleave_unit_size = rank_capacity / number_of_interleave_units), the system adapts the interleaving parameters to match the actual hardware configuration, improving efficiency for asymmetric ranks.
2Productivity
If current DRAM rank interleaving schemes allocate unused interleaving blocks, then all interleaving blocks are assigned, but refresh power consumption increases due to partial array self-refresh and auto-refresh overhead
Solution Approach 1:
The patent extracts and removes unused or partially used interleaving blocks from the active interleaving scheme. By identifying ranks that do not require full interleaving coverage and excluding them from the interleaving calculation, the system reduces the number of active interleaving blocks, thereby reducing refresh power consumption while maintaining necessary memory coverage.
Solution Approach 2:
The patent applies partial action by implementing interleaving only for the necessary portion of DRAM ranks. Instead of forcing full interleaving coverage across all ranks, the system calculates the optimal number of interleaving blocks needed based on actual rank sizes and usage patterns, applying interleaving partially where beneficial and avoiding it where unnecessary, thus reducing refresh overhead.
Data Source
AI summary
Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.