Asymmetric Dual Path Processor Architecture for Speed and Adaptability
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Solution Overview
Problem
Conventional dual execution path processors face limitations in speed and efficiency due to the lack of semantic content in 16-bit encoding and the inability to match application-specific algorithms for operations like convolution and Fast Fourier Transforms, despite using SIMD processing.
Innovation Solution
A computer processor with asymmetric dual execution paths, featuring a control processing channel with a narrower bit width and a data processing channel with a wider bit width, capable of executing control and data instructions separately, utilizing a decode unit to distinguish between control and data instructions and control their execution accordingly, with a configurable deep execution unit for enhanced parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dual execution paths with SIMD processing are used, then processor speed is increased, but the lack of semantic content in 16-bit encoding and inability to match application-specific algorithms limits further speed improvement
Solution Approach 1:
The processor is divided into two separate execution paths: a control execution path for sequential control instructions and a data execution path for parallel data processing instructions. This segmentation allows each path to be optimized for its specific function, with the data path capable of executing application-specific algorithms while the control path handles general control flow, thereby resolving the contradiction between speed and adaptability.
Solution Approach 2:
The control execution path and data execution path are designed with asymmetric characteristics - the control path uses narrower bit width for control instructions while the data path uses wider bit width for data processing instructions. This asymmetry enables the data path to accommodate application-specific algorithms with richer semantic content while maintaining high-speed parallel processing capabilities.
2Ease of manufacture
If two substantially identical channels are used for both control code and datapath code, then implementation is simplified, but processor speed and efficiency are limited due to redundancy in instruction encoding
Solution Approach 1:
Each execution path is given different local qualities suited to its function: the control execution path is designed with narrower bit width and sequential processing characteristics appropriate for control instructions, while the data execution path is designed with wider bit width and parallel processing characteristics appropriate for data processing instructions. This local quality differentiation eliminates encoding redundancy and improves overall processor efficiency while maintaining implementation feasibility.
Data Source
AI summary
According to embodiments of the invention, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embodiment according to the invention, there is provided a computer processor, the processor comprising: a decode unit for decoding instruction packets fetched from a memory holding a sequence of instruction packets; and first and second processing channels, each channel comprising a plurality of functional units, wherein the first processing channel is capable of performing control operations and comprises a control register file having a relatively narrower bit width, and the second processing channel is capable of performing data processing operations at least one input of which is a vector and comprises a data register file having a relatively wider bit width. The decode unit is operable to detect for each instruction packet whether the instruction packet defines (i) a plurality of control instructions to be executed sequentially on the first processing channel or (ii) a plurality of instructions comprising at least one data processing instruction to be executed simultaneously on the second execution channel, and to control the first and second channels in dependence on said detection.