Asymmetric Dual-Side Module Layout for Low-Stress Heat Dissipation

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Solution Overview

Problem

Existing power semiconductor packages face challenges in efficiently managing heat dissipation and stress distribution due to the stacking of substrates and heat sinks, leading to potential damage and reduced performance.

Innovation Solution

The implementation of a semiconductor package design featuring asymmetrically coupled substrates through spacers and a lead frame, with exposed sides for heat dissipation, and the use of conductive clips and spacers to reduce stress and enhance thermal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If substrates are stacked with heat sinks coupled to external terminals, then heat dissipation capability is improved, but stress concentration on internal components increases

Engineering Contradiction:
Improveheat dissipation capabilityVSAvoidstress concentration on internal components
Core Design Contradiction:
TemperatureVSStress or pressure

Solution Approach 1:

The patent employs asymmetric coupling of substrates through spacers, where the first substrate is coupled to the lead frame at a first location and the second substrate is coupled at a second location that is offset from the first location. This asymmetric arrangement distributes stress more evenly across the package structure, preventing stress concentration at single points while maintaining effective heat dissipation pathways through the substrates and heat sinks.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent introduces spacers as intermediary elements between the substrates and lead frame. These spacers act as stress-distributing mediators that mechanically couple the substrates to the lead frame while reducing direct stress transmission to sensitive internal components. The spacers provide a compliant interface that absorbs thermal and mechanical stresses.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If multiple substrates are stacked to increase power handling, then device functionality is improved, but structural integrity is compromised due to stress

Engineering Contradiction:
Improvepower handling capabilityVSAvoidstructural integrity
Core Design Contradiction:
PowerVSStrength

Solution Approach 1:

The asymmetric coupling arrangement with offset coupling locations allows the stacked substrates to be mechanically supported at different positions, distributing loads more effectively throughout the structure. This prevents stress concentration that would compromise structural integrity while enabling multiple substrates to be stacked for increased power handling capability.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent segments the coupling function across multiple locations and uses separate spacers for each substrate coupling. This segmentation of the mechanical coupling system allows each substrate to be independently supported and stressed, preventing cumulative stress effects that would compromise overall structural integrity while maintaining the stacked configuration for power handling.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design reduces stress on internal components, improves heat dissipation, and maintains structural integrity, thereby enhancing the performance and reliability of the semiconductor package.

Implementation Method 1

The design reduces stress on internal components

Methodology Applied
Scientific EffectStress distribution:

Implementation Method 2

improves heat dissipation

Methodology Applied
Scientific EffectHeat dissipation:

Implementation Method 3

the use of conductive clips and spacers to reduce stress and enhance thermal management

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20250323222A1Low stress asymmetric dual side module
Publication Date: 2025.10.16 SEMICON COMPONENTS IND LLC
  • US20250323222A1 patent drawing
  • US20250323222A1 patent drawing
  • US20250323222A1 patent drawing

AI summary

Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.