Asymmetric Dummy Gate Strip for FinFET Wet Cleaning Peeling
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Solution Overview
Problem
The peeling issue of dummy gate strips during wet cleaning processes in the gate replacement process of FinFETs leads to a low yield rate in semiconductor device fabrication.
Innovation Solution
The method involves forming first and second dummy gate strips with different lengthwise directions, where the first dummy gate strip is penetrated by the semiconductor fin and the second dummy gate strip is not, and includes a broadened portion on the dielectric layer, which reduces the peeling possibility and enhances the process window during gate replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy gate strips are used in the gate replacement process of FinFETs, then the gate replacement can be performed, but peeling issue occurs during wet cleaning processes leading to low yield rate
Solution Approach 1:
The dummy gate strip is designed with an asymmetric structure where one end has a first width and the other end has a second width that is different from the first width. This asymmetric width design prevents uniform peeling during wet cleaning processes, as the varying width creates different adhesion characteristics at each end, thereby reducing peeling issues and improving yield rate
Solution Approach 2:
The dummy gate strip exhibits local quality variation through its non-uniform width along its length. Different sections of the dummy gate strip have different widths, creating localized variations in adhesion properties. This allows certain regions to maintain stronger attachment during wet cleaning while other regions can be more easily removed, solving the peeling problem
2Device complexity
If conventional dummy gate strips are used, then the process is simple, but the process window is limited and peeling occurs
Solution Approach 1:
The asymmetric width design of the dummy gate strip expands the process window by providing different adhesion characteristics at each end. This structural variation allows the process to accommodate a wider range of cleaning conditions and parameters without causing peeling, thereby increasing adaptability while maintaining reasonable structural complexity
Data Source
AI summary
A semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. A lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin. The gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin. The second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.