Asymmetric Dummy Memory Cell Configuration for NAND Flash Reliability
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Solution Overview
Problem
NAND flash memory devices face operational challenges due to differences in electrical characteristics between memory cells adjacent to the bit line and those adjacent to the common source line, affecting memory cell operations.
Innovation Solution
The semiconductor device incorporates a memory block structure with a greater number of dummy memory cells connected to the bit line than to the common source line, along with a specific arrangement of main and dummy memory cells between the bit line and common source line, utilizing operation circuits to perform program, read, and erase loops efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are arranged between bit line and common source line, then memory device can be formed, but electrical characteristics differ between cells adjacent to bit line and cells adjacent to common source line
Solution Approach 1:
The patent applies local quality by creating asymmetric dummy memory cell configurations: more dummy memory cells are connected to the bit line than to the common source line. This local differentiation compensates for the inherent electrical characteristic differences between cells adjacent to the bit line and those adjacent to the common source line, achieving more uniform operational characteristics across all memory cells.
Solution Approach 2:
The patent employs asymmetry by intentionally designing an unequal number of dummy memory cells on each side of the main memory cells. Specifically, the bit line side has more dummy memory cells than the common source line side, creating an asymmetric structure that balances the electrical characteristics and improves overall reliability.
2Reliability
If dummy memory cells are added to balance electrical characteristics, then reliability improves, but device complexity increases
Solution Approach 1:
The patent changes the parameter of dummy memory cell quantity asymmetrically - increasing the number of dummy memory cells on the bit line side relative to the common source line side. This parameter adjustment optimizes electrical characteristics without requiring fundamental structural changes to the memory device architecture.
Data Source
AI summary
A semiconductor device includes a first memory string and a second memory string. The first memory string includes a plurality of first main memory cells formed on a pipe transistor of a semiconductor substrate and a plurality of first dummy memory cells connected between the first main memory cells and a common source line. The second memory string includes a plurality of second main memory cells formed on the pipe transistor and a plurality of second dummy memory cells connected between the second main memory cells and a bit line. The number of the second dummy memory cells is greater than the number of the first dummy memory cells.