Asymmetric E-Beam Lithography for Semiconductor Patterning
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Solution Overview
Problem
As semiconductor devices miniaturize, achieving high resolution in e-beam lithography becomes challenging due to the need for finer line widths and spaces, making it difficult to obtain precise patterns in a simplified and convenient process.
Innovation Solution
The method involves forming multiple mask patterns in a computer system, identifying critical and non-critical edges, and using asymmetry control to selectively adjust the electron beam lithography process, ensuring precise control over the critical edges while allowing more flexibility in the process window for other patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography is used for patterning, then the process is simplified and convenient, but the resolution is insufficient for fine-sized devices
Solution Approach 1:
The patterning process is divided into multiple steps: forming a first target pattern, forming a second target pattern across the first pattern, forming a hard mask layer, and performing asymmetric e-beam lithography to form a third pattern. This segmentation allows each step to be optimized independently, achieving high resolution while maintaining process manageability
Solution Approach 2:
The first and second target patterns are formed in advance using conventional lithography before the final e-beam lithography step. This preliminary action prepares the substrate with pre-defined patterns that guide the subsequent high-resolution e-beam patterning, reducing the complexity of the overall process
2Manufacturing precision
If e-beam lithography is used to achieve high resolution, then fine-sized devices can be obtained, but the process becomes more complex and less convenient
Solution Approach 1:
Asymmetric e-beam lithography is applied selectively: the first e-beam exposure forms patterns with high precision on one side (critical edge), while the second e-beam exposure forms patterns with relaxed precision on the opposite side (non-critical edge). This local differentiation of quality requirements reduces overall process complexity while maintaining necessary precision
Solution Approach 2:
The patent introduces asymmetric control in e-beam lithography by treating opposite edges of patterns differently. The critical edge receives full asymmetric control with stringent CD/AA specifications, while the non-critical edge allows greater process variation. This asymmetry reduces process complexity by eliminating unnecessary precision requirements for non-critical features
3Manufacturing precision
If asymmetric control is applied to all edges, then all patterns achieve high precision, but the process window is reduced
Solution Approach 1:
Different precision requirements are assigned to different edges: critical edges require asymmetric control with high precision, while non-critical edges allow symmetric control with greater process window. This local quality differentiation maintains necessary precision for critical features while preserving process flexibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor structures with precise and reliable patterns, particularly in contact slot formation, by optimizing the critical edge precision and process window, thus simplifying the patterning process while maintaining high resolution.
Implementation Method 1
an e-beam is used to delineate the features of a semiconductor by selectively irradiating a substrate coated with an e-beam sensitivity resist
Data Source
AI summary
A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.