Asymmetric Epitaxial Source/Drain Structures for Lower Parasitic Capacitance
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Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of integrated circuits to the 10 nanometer node or sub-10 nanometer range, necessitating new methodologies for multi-gate transistors, particularly in bulk silicon substrates, to optimize performance and reduce parasitic capacitance and resistance.
Innovation Solution
Implementing asymmetric epitaxial source or drain arrangements with differentiated gate spacers and contact processing, including backside power delivery and self-aligned access features, to enhance transistor performance by reducing parasitic capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or sub-10 nanometer range
Solution Approach 1:
The fabrication process is divided into separate stages: forming first and second epitaxial source or drain structures with different depths, then selectively removing portions to create asymmetric configurations. This segmentation allows precise control at 10nm node by breaking down complex patterning into manageable steps.
Solution Approach 2:
Different regions of the transistor are given different properties through asymmetric epitaxial growth - the first source or drain structure has different depth and doping characteristics than the second, optimizing local electrical properties for specific performance requirements while maintaining overall device functionality.
2Object-generated harmful factors
If symmetric epitaxial source or drain structures are used, then manufacturing simplicity is maintained, but parasitic capacitance increases
Solution Approach 1:
The patent implements asymmetric epitaxial source or drain structures where the first and second structures have different depths, widths, or doping concentrations. This asymmetry reduces parasitic capacitance between the source/drain and gate by creating non-uniform electric field distributions, directly addressing the harmful electrostatic effects in scaled devices.
Solution Approach 2:
The invention introduces depth as an additional dimension for differentiation beyond the planar dimensions. By controlling the vertical depth of epitaxial structures independently from lateral dimensions, the patent creates three-dimensional asymmetry that effectively reduces parasitic capacitance without complicating planar patterning processes.
3Power
If deeper contact structures are formed for backside power delivery, then power delivery capability is improved, but contact resistance increases
Solution Approach 1:
The patent performs preliminary doping and epitaxial growth of source and drain structures before final contact formation. This preliminary action ensures that the contact regions are pre-optimized with appropriate doping concentrations and crystal orientations, reducing contact resistance even when deep contacts are required for backside power delivery.
Solution Approach 2:
The invention changes material and structural parameters - using different epitaxial growth conditions, doping concentrations, and crystal orientations for different contact regions. These parameter changes enable deep contacts to maintain low resistance by optimizing the electrical properties of the contact path through controlled variations in material composition and structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves lower parasitic capacitance, improved contact resistance, and reduced short channel effects, enabling higher performance and efficiency in integrated circuits.
Implementation Method 1
forming a first epitaxial source or drain structure over a first conductive material and forming a second epitaxial source or drain structure over a second conductive material
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3
AI summary
Integrated circuit structures having asymmetric epitaxial source or drain arrangements are described. An integrated circuit structure (150) includes a gate stack (158, 156) over a plurality of horizontally stacked nanowires (154). A first epitaxial source or drain structure (160) is at a first end of the plurality of horizontally stacked nanowires (154). A first gate spacer (164A) laterally between the gate stack (158, 156) and the first epitaxial source or drain structure (160). A second epitaxial source or drain structure (162) is at a second end of the plurality of horizontally stacked nanowires (154). A second gate spacer (164B) is laterally between the gate stack (158, 156) and the second epitaxial source or drain structure (162). The first gate spacer (164A) has a width less than the second gate spacer (164B) by an amount of 10% or greater. In another embodiment the tips (260A) of the first epitaxial source or drain structure (260) have a greater lateral width than the tips (262A) of the second epitaxial source or drain structure (262), also by an amount of 10% or greater.