Asymmetric Eye Scan for Memory Signal Integrity
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Solution Overview
Problem
High-speed digital signal transmissions between memory controllers and modules face challenges in signal integrity and efficiency due to reflections and distortions caused by shared bi-directional data buses, leading to asymmetric eye shapes and reduced system margins.
Innovation Solution
A method involving a fast eye scan technique to identify optimal sampling locations by shifting the DQS position and running memory built-in self tests (BIST) to determine spatial regions on the eye, allowing for improved signal margins and noise tolerance, enabling faster data transfer rates and increased memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common bi-directional data bus is used to transfer information between memory controller and multiple DIMM modules, then device complexity is reduced, but signal integrity deteriorates due to reflections and distortions causing asymmetric eye shapes
Solution Approach 1:
The patent performs preliminary eye scan measurements during the initialization process to characterize the asymmetric eye shape distortion before normal operations. By pre-identifying the distortion pattern and selecting optimal sampling points in advance, the system compensates for the signal integrity issues caused by the shared bi-directional bus without requiring complex real-time correction mechanisms.
2Productivity
If signal transmission speed is increased to improve productivity, then data transfer rate increases, but signal integrity becomes more difficult to maintain due to reflections and distortions
Solution Approach 1:
The patent dynamically adjusts the sampling point selection based on the measured asymmetric eye shape characteristics. By making the sampling point adaptive rather than fixed, the system can maintain reliable data reception even at higher transmission speeds where the asymmetric distortion becomes more pronounced. This dynamic adjustment allows the system to operate at higher productivities while compensating for the degraded signal integrity.
3Reliability
If optimal sampling locations are identified through fast eye scan to improve signal margins, then reliability increases, but initialization time increases
Solution Approach 1:
The patent implements a fast eye scan that performs partial measurements at selected critical points rather than exhaustive measurements across the entire eye diagram. By focusing measurements only on the essential sampling locations needed to characterize the asymmetric distortion, the system achieves sufficient signal margin optimization without the time penalty of complete eye diagram analysis, thus balancing reliability improvement with acceptable initialization time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances system reliability and memory performance by identifying optimal sampling locations, increasing bandwidth and tolerating more noise, allowing configurations like 3DPC to reach 768 GB and 1866 MT/S, while maintaining efficient system boot times.
Implementation Method 1
subjecting an interface of a target DIMM module to a reflection caused by the signal propagation from other DIMM modules sharing the common bi-directional interface data bus to cause an introduction of distortion into a shape of an eye characterizing a signal
Data Source
AI summary
Techniques for processing signal information from a high speed communication bus. The techniques includes determining spatial regions on an eye characterized by a start point, an end point, a middle point, a left point, and a right point. The start point is a beginning of an eye opening at a reference voltage. The end point is at an ending of eye opening at the reference voltage. The middle point is at a center point of eye opening at the reference voltage. The left point is a left sampling location characterized by a minimum setup time requirement, and the right point is a right sampling location characterized by a minimum hold time requirement. Determining the points is based on shifting a DQS position and a DQ position and running a plurality of memory built-in self test (BIST) engines and a plurality of results of BIST tests.