Fin-Type Semiconductor Device With Asymmetric Gate Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with split gate cells, the uneven distribution of electrons and holes during write and erase operations leads to deteriorated retention characteristics due to the shape of the charge storage unit, especially when the control and memory gate electrodes straddle a fin, causing an increase in holes in the insulating film over time.
Innovation Solution
A semiconductor device design with a projecting portion on the substrate, featuring a fin-type structure where the control and memory gate electrodes are arranged to straddle the fin, with specific surface and side surface configurations to align the electron and hole distributions during writing and erasing, and a manufacturing method to form these electrodes and insulating films to enhance charge storage unit efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the control gate electrode and memory gate electrode straddle a fin structure, then the memory cell can be formed with split gate configuration, but the distribution of electrons and holes injected into the charge storage unit becomes uneven, causing deterioration of retention characteristics
Solution Approach 1:
The patent introduces an asymmetric structure by forming a recess in the fin at a position different from the center in the channel width direction. This asymmetric recess position creates different distances from the control gate electrode and memory gate electrode to the charge storage unit, thereby equalizing the electron and hole injection distributions despite the split gate configuration.
Solution Approach 2:
The patent applies local quality by creating a recess only in specific regions of the fin structure. The recess is formed at a predetermined position in the channel width direction, allowing localized modification of the fin geometry to control charge distribution without affecting the entire fin structure uniformly.
2Productivity
If write and erase operations are repeated a large number of times with uneven charge distribution, then data can be stored and erased, but the number of holes remaining in the insulating film increases, deteriorating memory cell characteristics
Solution Approach 1:
The asymmetric recess position compensates for the uneven charge injection that occurs during repeated write and erase operations. By creating different path lengths for electron and hole injection through the asymmetric fin structure, the patent reduces cumulative hole accumulation in the insulating film, maintaining memory cell characteristics over multiple operation cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the performance of semiconductor devices by aligning electron and hole distributions, reducing hole retention in the insulating film and enhancing memory cell characteristics, thereby improving data retention and operational efficiency.
Implementation Method 1
data is written by injecting electrons into the charge storage unit inside the insulating film
Implementation Method 2
an insulating film having a charge storage unit inside is formed
Data Source
AI summary
A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction.