Asymmetric Flash Memory Cell Gates for Decoupled Program Erase
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Solution Overview
Problem
Existing memory cells, particularly flash memory cells, face challenges in optimizing program and erase efficiency due to the antagonistic nature of floating gate overlap distances, which limits scaling and increases voltage requirements, and asymmetrical overlaps in multi-floating gate cells lead to manufacturing imperfections.
Innovation Solution
The memory cell design decouples the program and erase gates, allowing for asymmetrical overlap between the word line and erase gate relative to the floating gate, enabling independent optimization of program and erase coupling by varying the overlap distances, thereby minimizing program current and maximizing erase current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a common program/erase gate is used with symmetrical overlap, then manufacturing is simplified, but program and erase efficiency cannot be independently optimized
Solution Approach 1:
The common program/erase gate is segmented into two separate gates: a word line for programming and an erase gate for erasing. This segmentation allows each gate to have independent overlap distance with the floating gate, enabling separate optimization of program and erase efficiency while maintaining manufacturing simplicity through standardized fabrication processes
Solution Approach 2:
The patent introduces asymmetry in the overlap distances between gates and floating gate. The word line has a first overlap distance while the erase gate has a second overlap distance that differs from the first. This asymmetric configuration enables independent optimization of program current (through word line overlap) and erase current (through erase gate overlap), resolving the contradiction between manufacturing simplicity and operational efficiency
2Area of moving object
If cell size is reduced for scaling, then device density is improved, but program and erase voltages must be increased
Solution Approach 1:
The asymmetric overlap configuration allows the erase gate to have enhanced coupling (larger overlap) to the floating gate, which compensates for the reduced cell size. This stronger erase coupling enables effective erasing at lower voltages in scaled-down cells, while the word line maintains appropriate overlap for programming operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the difference between program and erase state currents, improving cell performance and efficiency, and allows for independent control of floating gate and oxide cap thickness, reducing unwanted coupling and increasing erase current significantly.
Implementation Method 1
the extent to which the word line and erase gate overlap the floating gate is asymmetrical... allowing the program and erase coupling to the floating gate to be optimized independently
Data Source
AI summary
A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.