Asymmetric Floating Gate Memory Bitcell with Decoupled Capacitor
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Solution Overview
Problem
Current nonvolatile memory bitcells face challenges in reducing size and cost due to the need for additional steps beyond standard CMOS processes, with eFLASH having small but costly bitcells and EEPROM having large bitcells unsuitable for high bit count memories.
Innovation Solution
A nonvolatile memory bitcell design with active regions capacitively coupled to a floating gate but electrically decoupled from the source and drain, allowing for efficient channel hot electron injection and impact ionized hot electron injection, reducing the size of the charge pump and bitcell, and enabling operation by band-to-band tunneling depending on applied voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If eFLASH bitcell design is used, then bitcell size is reduced, but manufacturing cost increases due to additional process steps beyond standard CMOS
Solution Approach 1:
The bitcell is segmented into distinct functional regions: a first active region containing source and drain, a second active region separated by a nonconductive region, and a floating gate spanning both regions. This segmentation allows the capacitor to be formed between the floating gate and second active region while keeping the source and drain electrically isolated, enabling efficient hot electron injection without requiring additional process steps beyond standard CMOS.
Solution Approach 2:
Different regions of the bitcell are given different electrical properties: the first active region contains the source and drain for current flow, the second active region serves as the capacitor plate, and the nonconductive region provides electrical isolation. This local differentiation of electrical characteristics enables the bitcell to achieve both small size and compatibility with standard CMOS manufacturing processes.
2Ease of manufacture
If EEPROM bitcell design is used, then compatibility with standard CMOS processes is maintained, but bitcell size becomes large making it unsuitable for high bit count memories
Solution Approach 1:
The capacitor is merged with the transistor structure by forming it between the floating gate and the second active region, rather than using a separate discrete capacitor. This integration eliminates the need for additional capacitor contacts and reduces the overall bitcell area while maintaining compatibility with standard CMOS processes.
Solution Approach 2:
The bitcell layout transitions from a planar arrangement to a three-dimensional structure where the floating gate extends over both the first and second active regions. This vertical utilization of space allows the capacitor to be formed within the same footprint as the transistor, significantly reducing the bitcell area while maintaining CMOS compatibility.
3Ease of operation
If separate capacitor contacts are included in the bitcell, then voltage control over the floating gate is improved, but the space requirements increase
Solution Approach 1:
The second active region serves multiple functions: it acts as the capacitor plate for voltage control, provides electrical isolation from the source and drain, and can be used for both read and write operations. This multi-functionality eliminates the need for separate capacitor contacts, achieving good voltage control while minimizing the bitcell area.
Solution Approach 2:
The nonconductive region acts as an intermediary between the first and second active regions, providing electrical isolation while allowing the floating gate to span both regions. This intermediary structure enables the capacitor to be formed without requiring separate capacitor contacts, thus reducing the bitcell area while maintaining voltage control capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the size and cost of bitcells by improving voltage control and eliminating the need for a charge pump in some cases, allowing for more efficient and flexible operation while maintaining compatibility with standard CMOS processes.
Implementation Method 1
A capacitor is formed by a first plate consisting of the portion of the floating gate above the second active region, and a second plate consisting of the portion of the second active region underneath the floating gate
Implementation Method 2
allows channel hot electron injection (CHEI) or impact ionized hot election injection (IHEI) to be performed with much higher efficiency
Implementation Method 3
allows channel hot electron injection (CHEI) or impact ionized hot election injection (IHEI) to be performed with much higher efficiency
Implementation Method 4
The bitcell may also be operated by CHEI (or IHEI) and separately by band-to-band tunneling (BTBT) depending upon the voltages applied at the source, drain, and capacitors
Data Source
AI summary
A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.