Asymmetric Floating Gate Memory Cell Erase Performance
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Solution Overview
Problem
Manufacturing split gate memory cells with a very thin floating gate structure is challenging due to potential damage to the underlying semiconductor material, which affects the erase performance of flash memory cells.
Innovation Solution
A memory cell design featuring a substrate with distinct regions, a word line, an erase gate, a floating gate with a non-uniform lateral distance between its ends, and a coupling gate, which enhances the erase gate-floating gate coupling ratio by focusing the electric field and maintaining a low capacitance, thereby improving erase performance without damaging the semiconductor material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating gate structure is made thinner to reduce the erase gate-floating gate coupling ratio, then the erase performance is improved, but the underlying semiconductor material may be damaged during manufacturing
Solution Approach 1:
The floating gate is designed with asymmetric thickness: a first thickness in the region between the erase gate and substrate, and a second thickness (greater than the first) in the region between the coupling gate and substrate. This asymmetric structure allows the floating gate to be thin near the erase gate (improving erase performance) while being thicker near the coupling gate (protecting against manufacturing damage).
Solution Approach 2:
Different regions of the floating gate have different thicknesses tailored to their specific functional requirements. The region adjacent to the erase gate has a thinner profile to enhance erase performance, while the region adjacent to the coupling gate has a thicker profile to provide manufacturing robustness. This local differentiation resolves the contradiction between performance and manufacturability.
2Reliability
If the floating gate structure is made thinner to improve erase performance, then the erase gate-floating gate coupling ratio is reduced, but the manufacturing process becomes more challenging
Solution Approach 1:
The floating gate employs asymmetric thickness distribution, being thinner near the erase gate and thicker near the coupling gate. This design achieves the desired low coupling ratio for improved erase performance while maintaining sufficient thickness in the coupling gate region to facilitate reliable manufacturing processes.
Solution Approach 2:
The floating gate structure implements local quality variation with different thicknesses in different regions. The thinner region near the erase gate optimizes erase performance, while the thicker region near the coupling gate ensures manufacturability, thereby resolving the contradiction between performance optimization and manufacturing ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the erase performance of flash memory cells by increasing the electric field between the erase gate and floating gate, facilitating faster electron flow while maintaining a low coupling ratio, thus improving the reliability and efficiency of the memory cell fabrication process.
Implementation Method 1
increasing the electric field between the erase gate and floating gate, facilitating faster electron flow
Data Source
AI summary
According to various embodiments, a memory cell may include a substrate of a first conductivity type, the substrate having first and second regions of a second conductivity type spaced apart and defining a channel region therebetween. The memory cell may further include a word line arranged over a portion of the channel region nearer to the first region, an erase gate arranged over the second region, a floating gate arranged over another portion of the channel region nearer to the second region and between the word line and the erase gate, and a coupling gate arranged over a top end of the floating gate. The floating gate includes the top end, a bottom end, a first side extending from the top end to the bottom end and facing the erase gate, and a second side extending from the top end to the bottom end and facing the word line. A first lateral distance between the bottom end of the floating gate and the erase gate may be larger than a second lateral distance between the top end of the floating gate and the erase gate.