Asymmetric Floating Gate Enhances Flash Memory Erase Speed
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Solution Overview
Problem
Conventional split-gate flash memory cells have slow erase speeds due to the limitations of Fowler-Nordheim tunneling (FNT) compared to source-side injection (SSI), which affects the efficiency of data state changes in memory cells.
Innovation Solution
The implementation of an asymmetric floating gate profile with a concave sidewall surface neighboring the erase gate and a tip at the interface between the floating gate and the concave sidewall surface, enhancing the electric field strength and tunneling rate through the tunneling dielectric layer, thereby improving erase speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional planar floating gate sidewall surfaces are used, then the device structure is simple and easy to manufacture, but the erase speed is slow due to limitations of Fowler-Nordheim tunneling
Solution Approach 1:
The patent applies asymmetry by creating an asymmetric floating gate profile where one sidewall surface is concave and the other is planar. The concave sidewall surface facing the erase gate creates a tip region with concentrated electric field, enhancing Fowler-Nordheim tunneling efficiency and improving erase speed compared to conventional symmetric planar floating gate structures.
Solution Approach 2:
The patent utilizes curvature by forming a concave sidewall surface on the floating gate instead of a planar surface. This curved geometry creates a tip region where electric field lines concentrate, significantly enhancing the tunneling effect during erase operations and thereby improving erase speed.
2Productivity
If asymmetric floating gate profile with concave sidewall surface is implemented, then the erase speed increases due to enhanced electric field concentration, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies local quality by creating a concave sidewall surface only on the portion of the floating gate that faces the erase gate, while the other sidewall remains planar. This localized geometric modification concentrates the electric field enhancement effect precisely where it is needed for erase operations, improving erase speed without requiring complete restructuring of the entire floating gate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The asymmetric floating gate design significantly increases the erase speed of split-gate flash memory cells by concentrating electric fields and enhancing electron tunneling during erase operations, outperforming conventional memory devices with planar floating gate sidewall surfaces.
Implementation Method 1
Conventional split-gate flash memory cells have slow erase speeds due to the limitations of Fowler-Nordheim tunneling (FNT) compared to source-side injection (SSI)
Implementation Method 2
enhancing the electric field strength and tunneling rate through the tunneling dielectric layer
Data Source
AI summary
A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate. The floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, and a tip defined an interface of the concave sidewall surface and an upper surface of the floating gate. A control gate and a sidewall spacer are arranged over the upper surface of the floating gate. The control gate is laterally offset from the tip of the floating gate, and the sidewall spacer is laterally arranged between the control gate and the tip. A method for manufacturing the split-gate flash memory cell is also provided.