Asymmetric Floating Gate Structure for Flash Memory
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Solution Overview
Problem
Inter-cell interference in flash memory devices increases due to the wide area of the floating gate, leading to variations in threshold voltage and degraded device characteristics and uniformity, while reducing the width of the floating gate to mitigate this issue lowers the program speed.
Innovation Solution
The method involves forming isolation films with a shallow trench structure, creating a floating gate with a narrower top width than bottom width, and using a Profiled Self-Aligned floating Gate (PSAG) structure with rounded edge portions to reduce the floating gate area while maintaining the overlap area with the control gate, thereby reducing inter-cell interference without lowering program speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the width of the second polysilicon layer is reduced to reduce inter-cell interference, then cell distribution is reduced, but the coupling ratio is reduced and program speed is lowered
Solution Approach 1:
The patent applies asymmetry by forming the floating gate with different widths at the top and bottom. The second polysilicon layer has a narrower width than the first polysilicon layer, creating an asymmetric floating gate structure. This asymmetric design allows the top width to be reduced for lower inter-cell interference while the bottom width maintains sufficient coupling ratio for program speed, thus resolving the contradiction between cell distribution and program speed.
Solution Approach 2:
The patent applies local quality by varying the width of the floating gate at different locations. The floating gate has a wider bottom portion for strong coupling with the control gate and a narrower top portion for reduced inter-cell interference. This localized variation in geometry allows different regions of the floating gate to serve different functions, resolving the contradiction between maintaining program speed and reducing cell distribution.
2Manufacturing precision
If the area of the floating gate is reduced to reduce inter-cell interference, then cell distribution is reduced, but the overlap area between control gate and floating gate is reduced
Solution Approach 1:
The asymmetric floating gate structure with different top and bottom widths allows the overall area to be reduced while maintaining sufficient overlap area. The bottom width is maintained to ensure adequate coupling between control gate and floating gate, while the top width is reduced to lower inter-cell interference, thus resolving the contradiction between cell distribution and overlap area.
Solution Approach 2:
The patent resolves the area contradiction by transitioning from a uniform two-dimensional floating gate to a three-dimensional structure with varying cross-sectional dimensions. The floating gate has different widths at different heights, allowing area reduction in the horizontal dimension while maintaining overlap area in the vertical dimension, thus addressing both cell distribution and coupling requirements.
Data Source
AI summary
A flash memory device and method of fabricating the same, wherein a width at the top of a floating gate is narrower than that at the bottom of the floating gate. The area of the floating gate can be reduced while maintaining the overlap area between the control gate and the floating gate. Therefore, inter-cell interference can be reduced without lowering program speed.