Asymmetric Floating Gate Structure for Memory Write Potential Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory devices, the capacitive coupling ratio between the control gate and the floating gate, and the tunnel insulation layer affects the write potential required for charging the floating gate, leading to inefficiencies in charge injection and potential reduction, as the existing designs do not optimize the geometry of the floating gate and insulation layers for reduced coupling ratios.
Innovation Solution
The semiconductor memory device features a floating gate structure with a wider upper portion and a narrower lower portion, positioned between projecting insulation layers, with a dielectric layer covering the floating gate and control gate formed over the dielectric layer, optimizing the capacitive coupling ratio to reduce the write potential needed for charge injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the floating gate structure uses a conventional rectangular geometry, then the manufacturing process is simple, but the capacitive coupling ratio cannot be optimized to reduce write potential
Solution Approach 1:
The floating gate structure employs an asymmetric T-shaped geometry where the upper portion has a first width and the lower portion has a second width that is less than the first width. This asymmetric design optimizes the capacitive coupling ratio between the control gate and floating gate, enabling reduced write potential for charge injection while maintaining manufacturability through standard photolithography processes.
Solution Approach 2:
The invention introduces a dimensional variation by creating a T-shaped floating gate structure that extends differently in vertical and horizontal dimensions. The upper portion width differs from the lower portion width, utilizing dimensional optimization to improve capacitive coupling without adding manufacturing complexity.
2Productivity
If the capacitive coupling ratio is increased to reduce write potential, then charge injection efficiency improves, but the floating gate structure becomes more complex
Solution Approach 1:
The asymmetric T-shaped floating gate structure with different widths at upper and lower portions optimizes the capacitive coupling ratio Cr = Cip/(Cip+Ctun). This geometric asymmetry enhances charge injection efficiency by improving the coupling between control gate and floating gate, while the structure remains compatible with existing manufacturing processes.
3Use of energy by moving object
If the floating gate width is reduced at the lower portion, then the capacitive coupling ratio is optimized, but the structural stability may be compromised
Solution Approach 1:
The T-shaped floating gate structure maintains structural stability despite the width reduction at the lower portion by providing a broader upper portion that is supported by the narrower lower portion. This asymmetric design optimizes capacitive coupling while the broader upper section provides structural reinforcement.
Solution Approach 2:
The invention compensates for potential structural instability from width reduction by utilizing vertical dimension optimization. The T-shaped structure distributes mechanical stress across different vertical levels, with the upper portion providing structural support to the narrower lower portion connecting to the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the efficiency of charge injection into the floating gate by reducing the write potential required, allowing for effective operation with lower voltages and improved memory device performance.
Implementation Method 1
As Vfg rises, an electric field acting on the tunnel insulation layer increases, and this facilitates injection of electric charge into the floating gate
Implementation Method 2
A potential Vfg of the floating gate when a write potential Vcg is applied to the control gate is determined by capacitive coupling as represented by equations 1 and 2 below
Data Source
AI summary
In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.