Asymmetric Forksheet FET Layout for Drive Current and Cell Scaling
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Solution Overview
Problem
The challenge in gate-all-around nanosheet (GAA-NS) FET devices is maintaining a minimum separation between NMOS and PMOS devices to avoid capacitance and process-related complications, limiting cell area scaling, while conventional forksheet devices face issues with symmetric architectures leading to reduced drive current and stress-induced defects.
Innovation Solution
An asymmetric forksheet FET design is introduced, with a dielectric isolation barrier positioned asymmetrically to separate NMOS and PMOS devices, reducing NMOS width and increasing PMOS width, thereby minimizing parasitic capacitance and eliminating the need for additional stress to enhance hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional stress is applied to PMOS device to enhance hole mobility, then drive current is improved, but stress-induced defects occur
Solution Approach 1:
The patent applies asymmetry by providing an asymmetric forksheet FET device where the PMOS nanolayer structure has a greater width than the NMOS nanolayer structure. This asymmetric design inherently compensates for the lower hole mobility in PMOS without requiring additional stress, thereby improving drive current while avoiding stress-induced defects.
2Reliability
If sheet width of NMOS and PMOS devices is increased to increase drive current, then operational speed is enhanced, but gate and parasitic capacitance are amplified resulting in reduction in speed
Solution Approach 1:
The patent resolves this contradiction by implementing asymmetric width design where PMOS nanolayer structure has greater width than NMOS. This allows the PMOS device to achieve sufficient drive current with a moderate width increase, while the NMOS width is optimized to minimize parasitic capacitance. The asymmetric configuration balances drive current requirements against capacitance penalties, maintaining operational speed.
3Reliability
If minimum separation between NMOS and PMOS devices is maintained to avoid capacitance and process complications, then device reliability is improved, but cell area scaling is limited
Solution Approach 1:
The asymmetric forksheet design allows NMOS and PMOS nanolayer structures to be positioned on opposite sides of a centrally placed dielectric wall with asymmetric widths. This configuration reduces the spacing between devices while maintaining adequate separation to avoid capacitance and process complications, thereby enabling cell area scaling.
Data Source
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Figure 3~3C
AI summary
The disclosure relates a FET device (10), in particular a forksheet device. The FET device (10) comprises: a first nanolayer structure (11) which comprises one or more first channel layers (na-c); a second nanolayer structure (12) which comprises one or more second channel layers (12a-c); and a dielectric isolation barrier (13) which is arranged to separate the first nanolayer structure (11) from the second nanolayer structure (12), wherein the dielectric isolation barrier (13) is in direct contact with the first and the second nanolayer structure (12) and extends along a first axis; wherein a width of the first nanolayer structure (11) along a second axis, which is perpendicular to the first axis, is smaller than a width of the second nanolayer structure (12) along the second axis.