Asymmetric GAA Gate Structures for Stacked Transistor Routing
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Solution Overview
Problem
As integrated circuits scale down, stacking transistor devices vertically to increase density presents challenges in signal routing due to increased resistance and voltage drops across gate structures and contacts.
Innovation Solution
The implementation of asymmetric gate structures with a T-shaped or inverted T-shaped configuration, and elongated gate contacts that extend beyond the underlying gate surface, to reduce voltage drops and improve signal routing in stacked transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor devices are stacked vertically to increase density, then device density is improved, but signal routing resistance and voltage drops increase
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by extending gate contacts vertically through multiple transistor layers. This allows signals to reach upper transistor gates through vertical pathways rather than lateral routing, reducing the length and resistance of interconnect paths while maintaining high device density.
Solution Approach 2:
The gate contact structure is segmented into multiple portions, with each contact portion extending to a specific transistor layer. This segmentation allows optimized routing paths for different transistor levels, reducing overall signal resistance by providing direct vertical access to each gate rather than requiring long lateral connections through the substrate.
2Ease of manufacture
If symmetric gate structures are used in stacked transistors, then manufacturing simplicity is maintained, but voltage drops are excessive and signal integrity deteriorates
Solution Approach 1:
The patent employs asymmetric gate structures where gate contacts extend different distances vertically to reach different transistor layers. For example, in a three-transistor stack, the gate contact may extend to the first, second, and third transistors with varying contact lengths and positions. This asymmetry optimizes voltage distribution and reduces voltage drops across each transistor gate, improving signal integrity while remaining manufacturable through standard lithography and deposition processes.
Data Source
AI summary
Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.