Asymmetric GaN RF Transistor Layout for Lower On-Resistance
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Solution Overview
Problem
Group III nitride-based RF transistor amplifiers face a tradeoff between on-resistance and parasitic intrinsic capacitances, where reducing on-resistance increases parasitic capacitances, and vice versa, making it difficult to achieve high power handling and frequency operation without compromising gain and efficiency.
Innovation Solution
The design incorporates asymmetrical gallium nitride-based source/drain regions that extend farther towards each other, reducing on-resistance without increasing parasitic capacitances by replacing portions of the higher resistance channel region with lower resistance drain and source regions, thereby maintaining performance metrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain regions are widened to reduce on-resistance, then on-resistance decreases and power handling improves, but parasitic intrinsic capacitances increase which degrades frequency performance
Solution Approach 1:
The patent applies asymmetry by configuring the source and drain regions with different lateral extension distances. Specifically, the source/drain regions extend asymmetrically towards each other, with one side extending farther than the other. This asymmetric configuration reduces the total on-resistance while minimizing the increase in parasitic capacitances between the gate and source/drain regions, thereby resolving the technical contradiction between low on-resistance and low parasitic capacitance.
Solution Approach 2:
The patent implements local quality by creating non-uniform doping profiles and varying the lateral extension distances of source/drain regions at different locations. The source/drain regions have different doping concentrations and extension distances on different sides, allowing localized optimization of electrical properties. This enables reduced on-resistance in critical areas while maintaining lower parasitic capacitances in other regions, resolving the contradiction between power handling and frequency performance.
2Productivity
If source/drain regions extend farther towards each other to replace channel region, then on-resistance decreases and current handling improves, but device complexity increases
Solution Approach 1:
The asymmetric extension of source/drain regions provides an efficient method to enhance current handling capability without requiring symmetric complex structures. By extending source/drain regions asymmetrically, the patent achieves effective current paths with simpler overall device architecture compared to fully symmetric configurations, thus improving productivity while controlling device complexity.
Solution Approach 2:
The patent utilizes parameter changes by varying the lateral extension distances, doping concentrations, and geometrical dimensions of source/drain regions. These parameter optimizations allow the device to achieve high current handling capability through controlled modifications of source/drain region properties rather than through complex structural arrangements, thereby improving productivity while maintaining manageable device complexity.
Data Source
AI summary
A gallium nitride-based RF transistor amplifier comprises a semiconductor layer structure comprising a barrier layer on a channel layer, first and second source/drain regions in the semiconductor layer structure, first and second source/drain contacts on the respective first and second source/drain regions, and a longitudinally-extending gate finger that is between the first and second source/drain contacts. The first and second source/drain contacts each has an inner sidewall that faces the gate finger and an opposed outer sidewall. The first source/drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure, and extends a second, smaller distance from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region.


