Asymmetric Gate Capacitance in Capacitor-less DRAM
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Solution Overview
Problem
Capacitive coupling between the word line and the floating body in capacitor-less single-transistor DRAMs causes direct noise transmission, leading to erroneous reading or rewriting of storage data, making it difficult to commercially introduce such DRAMs.
Innovation Solution
A semiconductor memory device with a structure that includes a semiconductor base material on a substrate, impurity layers, gate insulating layers, and gate conductor layers, where the gate capacitance of one gate conductor layer is larger than the other, allowing for controlled page write and erase operations to minimize capacitive coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but capacitive coupling noise between word line and floating body increases causing erroneous reading or rewriting
Solution Approach 1:
The gate conductor layer is divided into two separate layers (first gate conductor layer and second gate conductor layer) with different capacitance values. This segmentation allows independent control of capacitive coupling effects, enabling the larger capacitance gate to dominate and suppress noise transmission to the floating body while maintaining high integration density through the capacitor-less single-transistor structure
Solution Approach 2:
The patent introduces asymmetric capacitance values between the two gate conductor layers, where one layer has significantly larger gate capacitance than the other. This asymmetry creates an imbalance in capacitive coupling that prevents direct noise transmission from the word line to the floating body, thereby improving data storage reliability while preserving the high-density benefits of the capacitor-less structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces capacitive coupling noise, providing a sufficient margin between data states and enabling reliable data storage in capacitor-less single-transistor DRAMs, facilitating their commercial introduction.
Implementation Method 1
Capacitive coupling between the word line and the floating body in capacitor-less single-transistor DRAMs causes direct noise transmission
Implementation Method 2
accelerated electrons that flow from the source N+ layer 103 toward the drain N+ layer 104 collide with the Si lattice, and with kinetic energy lost at the time of collision, electron-positive hole pairs are generated (impact ionization phenomenon)
Data Source
AI summary
A memory device includes a plurality of pages arranged in columns, each page is constituted by a plurality of memory cells arranged in rows on a substrate, the memory cells included in the page are memory cells of a plurality of semiconductor base materials that stand on the substrate in a vertical direction or that extend in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer, and all memory cells included in a first page subjected to the page erase operation perform the page write operation at least once.