Asymmetric Gate Cut Isolation for SRAM Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current self-aligned gate edge processes for forming gate cut isolations in integrated circuits, particularly in SRAMs, result in symmetrically spaced isolations that restrict N-to-P scaling and increase SRAM cell area requirements due to stringent lithographic tolerances, making it challenging to achieve efficient electrical isolation between adjacent FETs.
Innovation Solution
The method involves forming asymmetric gate cut isolations by creating a sacrificial liner over one active nanostructure, which shifts the gate cut isolation closer to the adjacent nanostructure, allowing for reduced space and improved scaling without increasing SRAM cell area, enabling more precise control over the isolation and reducing the need for extreme ultraviolet lithography techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If symmetrically spaced gate cut isolations are used in self-aligned gate edge processes, then electrical isolation between adjacent FETs is achieved, but SRAM cell area increases and N-to-P scaling is restricted
Solution Approach 1:
The patent applies asymmetry by forming the gate cut isolation at an asymmetric position between adjacent active nanostructures, specifically closer to the second active nanostructure than the first. This is achieved by selectively removing the protective layer from the first active nanostructure while leaving it intact on the second, allowing the gate cut isolation to be positioned asymmetrically in the space between them, thereby reducing SRAM cell area while maintaining electrical isolation
2Reliability
If symmetrically spaced gate cut isolations are used, then electrical isolation between adjacent FETs is achieved, but lithographic tolerances become extremely small
Solution Approach 1:
The asymmetric positioning of the gate cut isolation relaxes lithographic tolerances by eliminating the requirement for precise symmetric spacing. The protective layer removal process creates a self-aligned asymmetric structure that is less sensitive to lithographic variations, making manufacturing more robust
3Reliability
If symmetrically spaced gate cut isolations are used, then electrical isolation between adjacent FETs is achieved, but additional N-to-P scaling is restricted
Solution Approach 1:
The asymmetric gate cut isolation structure provides greater design flexibility for N-to-P scaling. By positioning the isolation asymmetrically, the patent enables more aggressive scaling of the distance between n-type and p-type active nanostructures without compromising electrical isolation, thus improving adaptability for future scaling nodes
Data Source
AI summary
Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.