Asymmetric Gate Driver Transistor for Display Bezel Reduction
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Solution Overview
Problem
The integration of the gate driver in display devices, such as LCDs and OLEDs, is limited by noise or ripple effects in gate driver signals, which restricts the reduction of the peripheral area and thus the bezel width of the display device.
Innovation Solution
The design includes a substrate with a driver circuit featuring thin film transistors and a capacitor, where the overlapping areas between the gate electrodes and the drain/source regions are asymmetrical, and a capacitor with a specific parasitic capacitance ratio, to reduce the area occupied by the capacitor and minimize signal ripple.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the gate driver is integrated in the display panel peripheral area, then the bezel width is reduced, but signal ripple and noise increase
Solution Approach 1:
The patent applies asymmetry by making the overlapping area between the first gate electrode and the drain region different from the overlapping area between the first gate electrode and the source region. Specifically, the overlapping area with the drain region is designed to be larger than that with the source region, creating an asymmetric configuration that balances parasitic capacitances and reduces signal ripple while maintaining compact integration in the peripheral area.
2Area of stationary object
If the peripheral area of the display panel is reduced, then the bezel width is reduced, but the gate driver cannot be properly disposed
Solution Approach 1:
The patent merges the gate driver circuit with the display panel by integrating it directly into the peripheral area of the display panel substrate. The gate driver transistors and capacitors are formed using the same thin film deposition and processing techniques as the pixel transistors, combining multiple functions into a single integrated structure that eliminates the need for separate chips or larger peripheral areas.
Solution Approach 2:
The patent utilizes vertical stacking in the peripheral area to accommodate the gate driver circuit. By arranging transistors and capacitors in multiple layers with overlapping gate electrodes and semiconductor regions, the design efficiently packs the gate driver functionality into a compact two-dimensional footprint on the display panel periphery.
3Length of moving object
If the capacitor area is reduced, then the gate driver width is reduced, but signal storage capability is compromised
Solution Approach 1:
The patent implements nesting by placing the capacitor structure within and around the transistor structure. The capacitor electrodes utilize overlapping regions of the gate electrodes and semiconductor layers, effectively nesting the capacitor functionality within the existing transistor footprint. This nested configuration provides adequate signal storage capacitance without increasing the overall gate driver width.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a reduction in the width of the gate driver and the bezel of the display device while preventing or reducing signal ripple, enabling a more compact display design.
Implementation Method 1
a first area formed by the overlapping portion of the first gate electrode and the drain region has a different size than a second area formed by the overlapping portion of the first gate electrode and the source region
Implementation Method 2
A ratio of the first parasitic capacitance to a sum of the second parasitic capacitance and the first capacitance may be equal to greater than about 1 to 8
Data Source
AI summary
A display device having a gate driver which may reduce generation of ripple at the output of the gate drive includes: a substrate; and a driver circuit including a thin film transistor disposed on the substrate, the thin film transistor including: a first gate electrode disposed on the substrate; a semiconductor layer disposed on the first gate electrode to overlap a part of the first gate electrode, the semiconductor layer including channel, source, and drain regions; a second gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer and respectively connected to the source region and the drain region, wherein a first area formed by the overlapping portion of the first gate electrode and the drain region has a different size than a second area formed by the overlapping portion of the first gate electrode and the source region.