Asymmetric Gate Driving Circuit for Reduced Bezel Area
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Solution Overview
Problem
The existing gate driving circuits for display devices, particularly in high-resolution panels, face challenges in reducing circuit size and bezel area while maintaining uniform image quality, as they increase in size with the number of gate lines, leading to inefficiencies in the GIP circuit's bezel area usage.
Innovation Solution
The proposed solution involves a gate driving circuit with asymmetrically connected first and second gate driving circuits to gate lines, each generating output voltages with different rising and falling times, allowing for shared Q node control of pull-up transistors, which reduces the overall circuit size and ensures uniform image quality across the display panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of gate lines increases to achieve higher display resolution, then the image quality improves, but the size of the gate driving circuit increases leading to larger bezel area
Solution Approach 1:
The gate driving circuit is divided into multiple independent shift register stages, where each stage controls a portion of the gate lines. This segmentation allows the circuit to be distributed across different regions of the display panel, reducing the concentration of circuit elements in any single bezel area and enabling higher resolution without proportionally increasing overall bezel size.
Solution Approach 2:
The gate driving circuit is extended from a single linear arrangement into a two-dimensional distributed structure across the display panel. By utilizing both horizontal and vertical dimensions for circuit placement, the design accommodates more gate lines without linearly increasing the bezel area, thus supporting higher resolution displays with controlled bezel dimensions.
2Adaptability or versatility
If the gate driving circuit size increases to support more gate lines, then the circuit can drive higher resolution displays, but the bezel area usage becomes less efficient
Solution Approach 1:
Each shift register stage is designed with universal functionality to control multiple gate lines through shared control signals and distributed output nodes. The stages can be configured to drive different numbers of gate lines depending on the display resolution requirements, allowing the same circuit architecture to adapt to various resolutions without proportionally increasing bezel area.
Solution Approach 2:
The gate driving circuit implements local quality by assigning different functional characteristics to different regions of the circuit. Each shift register stage is optimized for its specific position and gate line assignments, allowing efficient utilization of bezel area in each local region while maintaining overall adaptability to different display resolutions through the distributed architecture.
Data Source
AI summary
A gate driving circuit and a display device using the same are provided. The gate driving circuit includes a first gate driving circuit configured to sequentially generate first and second output voltages and a second gate driving circuit configured to sequentially generate first and second output voltages. The first gate driving circuit and the second gate driving circuit are asymmetrically connected to gate lines. The first output voltage of the first gate driving circuit is supplied to an nth gate line, and the second output voltage of the second gate driving circuit is supplied to the nth gate line.