Asymmetric Gate Electrode With Low-k Spacer
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Solution Overview
Problem
As semiconductor devices become highly integrated, leakage current through the gate insulation layer and parasitic capacitance between the gate electrode and contact plug pose challenges that existing technologies have not adequately addressed.
Innovation Solution
A semiconductor device design featuring a gate structure with a lower gate electrode, an upper gate electrode whose width increases from the bottom to the top, and inner spacers made of low-k dielectric material to surround the upper gate electrode and high-k dielectric layer, which helps in reducing leakage current and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-k dielectric layer is formed to surround the gate electrode to inhibit leakage current, then leakage current is reduced, but parasitic capacitance occurs between the gate electrode and adjacent contact plug
Solution Approach 1:
A low-k dielectric inner spacer is introduced as an intermediary layer between the gate electrode and the contact plug. This inner spacer acts as a mediator that reduces the parasitic capacitance formed between the gate electrode and the contact plug, while the high-k dielectric layer continues to provide leakage current inhibition. The low-k dielectric material has a lower dielectric constant than the high-k dielectric layer, thereby reducing the capacitive coupling between adjacent structures.
Solution Approach 2:
Different dielectric materials with different properties are used in different locations: a high-k dielectric layer is used where leakage current inhibition is needed (surrounding the gate electrode), while a low-k dielectric inner spacer is used where parasitic capacitance reduction is needed (between the gate electrode and contact plug). This local differentiation of material properties allows simultaneous optimization of both leakage current inhibition and parasitic capacitance reduction.
2Ease of operation
If the gate electrode width is increased to improve contact with the contact plug, then contact ease is improved, but the device area increases
Solution Approach 1:
The gate electrode is designed with an asymmetric width profile where the width varies along the vertical direction. The top portion of the gate electrode has a greater width than the bottom portion, allowing easier contact with the contact plug at the top where the contact is needed, while maintaining a narrower bottom portion to minimize the overall device area. This asymmetric geometry optimizes both contact ease and area efficiency.
Solution Approach 2:
Instead of increasing the gate electrode width uniformly in the horizontal plane (which would increase device area), the width variation is introduced in the vertical dimension. The gate electrode width changes from the bottom to the top, allowing contact optimization in the vertical direction without proportionally increasing the horizontal footprint of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively decreases leakage current and parasitic capacitance, maintaining desired electrical characteristics while allowing easy contact between the upper gate electrode and the contact plug.
Implementation Method 1
The first inner spacer may include a low-k dielectric material
Implementation Method 2
A high-k dielectric layer may be formed to surround a bottom and a sidewall of the gate electrode
Data Source
AI summary
A semiconductor device includes a gate insulation layer pattern, a lower gate electrode, an upper gate electrode, and a first inner spacer. The gate insulation layer pattern is formed on a substrate. The lower gate electrode is formed on the gate insulation layer pattern. The upper gate electrode is formed on the lower gate electrode and has a width that gradually increases from a bottom portion toward a top portion thereof. The width of the bottom portion of the upper gate electrode is smaller than a width of a top surface of the lower gate electrode. The first inner spacer surrounds a sidewall of the upper gate electrode.