Asymmetric Gate Field Effect Transistor Sidewall Channel Control
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Solution Overview
Problem
Conventional field effect transistors face challenges in effectively utilizing the sidewall of an active region protruding from a substrate as a channel, leading to reduced controllability and increased likelihood of short channel effects due to non-perpendicular slopes and varying widths of the gate electrode and source/drain regions.
Innovation Solution
The design incorporates a gate electrode with a lower width greater than an upper width, a concave-shaped sidewall, and source/drain regions with a lattice constant greater than the active region material, such as silicon-germanium, to create a sloped interface that allows for effective channel formation and reduces short channel effects by adjusting the sidewall profile of the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate electrode has a uniform width and perpendicular sidewalls, then the manufacturing process is simple, but the channel width control is poor and short channel effects increase
Solution Approach 1:
The gate electrode is designed with asymmetric dimensions where the lower width (at the substrate interface) is greater than the upper width. This asymmetric configuration allows the lower width to control the channel width for improved precision while the upper width can be optimized for other performance parameters, resolving the contradiction between manufacturing simplicity and channel width control.
Solution Approach 2:
The gate electrode transitions from a two-dimensional planar structure to a three-dimensional structure with varying width through its height. This dimensional change enables independent optimization of channel width control (via lower width) and other performance aspects (via upper width), addressing the technical contradiction.
2Reliability
If the source/drain regions have the same lattice constant as the active region, then the material compatibility is good, but charge mobility is limited
Solution Approach 1:
The source/drain regions are doped with silicon germanium to create a local variation in lattice constant and material properties. This local quality change in specific regions (source/drain) while maintaining the active region's original material enables enhanced charge mobility through strain effects without compromising the overall device compatibility.
3Productivity
If the active region sidewall is used as a channel, then the effective channel width increases, but the controllability decreases due to non-perpendicular slopes
Solution Approach 1:
The gate electrode's asymmetric width profile (lower width greater than upper width) is specifically designed to compensate for the non-perpendicular slope of the active region sidewall. The greater lower width ensures that the channel width at the substrate interface - where the sidewall slope exists - is properly controlled, maintaining manufacturing precision while utilizing the sidewall as an effective channel.
Data Source
AI summary
Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region. Source/drain regions are provided at both sides of the active region under the gate electrode, respectively. A width of a lower portion of the gate electrode is greater than a width of an upper portion of the gate electrode.