Asymmetric Gate Field Plate for High Breakdown Voltage
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Solution Overview
Problem
Traditional semiconductor field-effect transistors face a tradeoff between frequency performance and breakdown voltage due to high peak electric fields, which is exacerbated by the addition of field plates that introduce parasitic capacitance, making it difficult to achieve high yield and reproducibility in manufacturing, especially at sub-micron scales.
Innovation Solution
A field effect transistor structure with a buried, asymmetric field plate is created using a gate electrode with a stem section and dielectric spacers, where the bottom portion is narrower than the upper portion and has a step on one side, formed using standard optical lithographic techniques to minimize parasitic capacitance and enhance breakdown voltage without compromising frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If field plates are added to reduce peak electric field and enhance breakdown voltage, then breakdown voltage is improved, but parasitic capacitance increases which deteriorates frequency performance
Solution Approach 1:
The patent applies local quality by creating an asymmetric field plate structure where the field plate extends only on the drain side of the gate electrode, not on both sides. This localized approach concentrates the field-reducing effect precisely where the peak electric field occurs (at the drain-gate junction) while minimizing the addition of parasitic capacitance that would result from a symmetric field plate extending on both sides.
Solution Approach 2:
The patent directly applies asymmetry by designing the field plate to extend only on one side (drain side) of the gate electrode rather than symmetrically on both sides. This asymmetric configuration optimizes the reduction of peak electric field at the critical drain-gate interface while avoiding unnecessary parasitic capacitance on the source side, thereby resolving the contradiction between breakdown enhancement and frequency performance.
2Manufacturing precision
If traditional lithographic techniques are used to form nanometer-sized field plates, then manufacturing precision is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent merges the field plate formation process with the existing gate electrode fabrication process. The field plate is formed as an extension of the gate electrode using the same lithographic patterning step, eliminating the need for separate alignment and patterning processes. This integration maintains nanometer-scale precision while significantly reducing fabrication complexity and process steps.
Solution Approach 2:
The patent makes the gate electrode multi-functional by having it serve both as the control electrode and as the base structure for the field plate. The field plate is formed by extending part of the gate electrode material laterally, allowing a single structural element to perform both gate control and field management functions, thereby simplifying the overall device structure and fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach allows for reduced parasitic capacitance and enhanced breakdown voltage while maintaining frequency performance, enabling efficient fabrication of transistors with nanometer-sized field plates that are reproducible and cost-effective.
Implementation Method 1
a gate electrode having a stem section extending from a top section of the gate electrode to, and in Schottky contact with, the gate contact region
Data Source
AI summary
A field effect transistor structure having a semiconductor having a source region, a drain region, and a gate contact region disposed between the source region and the drain region; and a gate electrode having a stem section extending from a top section of the gate electrode to, and in Schottky contact with, the gate contact region. The stem section has an upper portion terminating at the top portion of the gate electrode and a bottom portion narrower than the upper portion, the bottom portion terminating at the gate contact region. The bottom portion of the stem has a step between the upper portion of the stem section and the bottom portion of the stem section in only one side of the stem section. The step of the stem section provides an asymmetric field plate for the field effect transistor.