Asymmetric Gate Fin Layout for Semiconductor Devices
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Solution Overview
Problem
The miniaturization of semiconductor devices poses challenges in fabricating fin field effect transistors (finFETs) due to the narrowing width of fin structures and shrinking spacing, which limits the process window and increases the complexity of forming gate structures that effectively cover the fin edges.
Innovation Solution
A layout and method where one gate completely covers both opposite edges of one fin and only one edge of another fin, allowing for an enlarged process window by forming a gate that crosses two adjacent fins, with a spacer covering the exposed edge of the partially covered fin, facilitating the formation of metal gates and reducing interference between adjacent gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a gate is formed to completely cover both opposite edges of one fin and only one edge of another fin, then the process window is enlarged and fabrication precision is improved, but the device structure becomes more complex
Solution Approach 1:
The gate structure is designed with non-uniform coverage: it completely covers both opposite edges of the first fin while covering only one edge of the second fin. This local differentiation in gate coverage creates asymmetric stress distribution that enlarges the process window for fabricating adjacent gates, directly improving manufacturing precision without requiring complex additional structures
Solution Approach 2:
The invention employs asymmetric gate-fin geometry where the gate extends across two adjacent fins but with different coverage degrees. The gate completely spans the first fin while partially covering the second fin, creating an asymmetric configuration that simplifies the fabrication process by providing a larger process margin for aligning adjacent gates
2Area of moving object
If the width of fin structures is narrowed and spacing is shrunk to achieve miniaturization, then device density is improved, but the process window decreases and fabrication becomes more difficult
Solution Approach 1:
The invention changes the geometric parameters of the gate-fin system by creating a configuration where the gate width relative to fin spacing produces asymmetric coverage. This parameter optimization allows the gate to completely cover one fin while partially covering the adjacent fin, providing an enlarged process window that compensates for the reduced dimensions achieved through miniaturization
Data Source
AI summary
A layout of a semiconductor device and a method of forming a semiconductor device, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.