Asymmetric Gate Insulating Layer for Low-Rsp LDMOS
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Solution Overview
Problem
LDMOS devices face a tradeoff between specific on-resistance (Rsp) and breakdown voltage (BV), with existing design approaches either increasing Rsp or decreasing BV, and existing field relief dielectrics like LOCOS and STI create weak points for breakdown and hot carriers.
Innovation Solution
The introduction of an asymmetric insulating layer with a smooth slope toward the source and a steeper slope away from the source, providing adjustable thickness and lateral scaling, which improves Rsp while reducing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing field relief dielectrics like LOCOS and STI are used, then device structure is simplified, but weak points for breakdown and hot carriers are created
Solution Approach 1:
The patent applies asymmetry by creating an insulating layer with different slopes on opposite sides - a first slope toward the source region and a second slope toward the drain region where the second slope is greater than the first slope. This asymmetric configuration eliminates the symmetry-induced weak points in conventional field relief dielectrics, preventing breakdown and hot carrier effects while maintaining structural simplicity.
2Ease of manufacture
If conventional symmetric insulating layers are used, then fabrication is simpler, but specific on-resistance increases and device area is larger
Solution Approach 1:
The asymmetric insulating layer configuration with different slopes on each side enables optimized electric field distribution that reduces specific on-resistance while maintaining manageable fabrication complexity through standard deposition and etching processes.
Solution Approach 2:
The patent introduces slope variation as an additional dimensional parameter in the insulating layer design, transitioning from a uniform thickness structure to one with controlled gradient profiles. This dimensional enhancement allows precise control of electric field distribution, achieving lower on-resistance without proportionally increasing device area.
3Area of stationary object
If conventional insulating layers are used, then device area is larger, but breakdown voltage control is less precise
Solution Approach 1:
By introducing slope as an additional design dimension, the patent achieves precise breakdown voltage control through the asymmetric profile. The different slopes on each side of the insulating layer enable fine-tuned electric field management, achieving superior voltage control with reduced device area compared to conventional uniform insulating layers.
Data Source
AI summary
Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a semiconductor layer, a source region disposed in the semiconductor layer, a drain region disposed in the semiconductor layer, a gate electrode, and an insulating layer disposed between a portion of the gate electrode and the semiconductor layer. The insulating layer has a first sidewall extending toward the source region and a second sidewall extending toward the drain region, the first sidewall having a first slope and the second sidewall having a second slope greater than the first slope.