Asymmetric Gate Electrode LDMOS Transistor
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Solution Overview
Problem
Conventional laterally-diffused metal-oxide semiconductor (LDMOS) transistors have high ON resistance due to large pitch and low carrier induction in the drift region, leading to low gain, power output, and efficiency.
Innovation Solution
An asymmetric gate electrode is introduced, laterally disposed between drain and source contact regions, extending into semiconductor regions with tilted sidewalls to induce additional carriers, reducing drift resistance and total ON resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistor structure is used, then device simplicity is maintained, but ON resistance is high due to large pitch and low carrier induction
Solution Approach 1:
The patent applies asymmetry by designing a gate electrode with non-uniform width along its length. The gate electrode comprises a first portion and a second portion with different widths, creating an asymmetric structure that optimizes the electric field distribution in the drift region. This asymmetric design allows for better carrier induction while maintaining manageable device complexity.
Solution Approach 2:
The patent transitions from a conventional planar gate structure to a three-dimensional asymmetric gate structure. The gate electrode extends in multiple dimensions with varying width, creating tilted sidewalls that interact with the drift region in a more complex spatial manner. This dimensional change enables improved electric field control and carrier induction without simply increasing pitch.
2Reliability
If larger pitch is used in conventional LDMOS, then device area increases, but ON resistance increases due to large pitch
Solution Approach 1:
The asymmetric gate electrode design allows for optimized electric field distribution that improves carrier induction efficiency. This enables reduction of ON resistance without requiring proportional increases in device area, as the asymmetric structure creates more effective use of the available space in the drift region.
Solution Approach 2:
The patent changes the geometric parameters of the gate electrode, specifically the width variation along its length. By adjusting the width of the first and second portions of the gate electrode, the design optimizes the electric field strength and carrier induction without simply scaling up the overall device area.
3Reliability
If conventional symmetric gate electrode is used, then manufacturing is simpler, but carrier induction in drift region is insufficient
Solution Approach 1:
The patent implements asymmetry in the gate electrode to improve carrier induction. The first portion and second portion have different widths, creating tilted sidewalls that enhance the electric field effect on the drift region. This asymmetric design can be fabricated using standard photolithography and etching processes, making it compatible with existing manufacturing capabilities.
Solution Approach 2:
The gate electrode is designed with different local properties - the first portion has a different width than the second portion. This local variation in geometry creates optimized electric field distribution at different locations along the gate, improving carrier induction in the drift region while maintaining overall structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The asymmetric gate electrode design enhances gain, power output, and efficiency by reducing drift resistance and total ON resistance, resulting in a higher performing LDMOS transistor.
Implementation Method 1
An asymmetric gate electrode is introduced, laterally disposed between drain and source contact regions, extending into semiconductor regions with tilted sidewalls to induce additional carriers, reducing drift resistance and total ON resistance.
Data Source
AI summary
A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.