Asymmetric Gate Patterns in 3D Semiconductor Memory
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high memory cell integration density due to limitations in gate pattern separation and insulation, which affect the cost and performance of three-dimensional semiconductor memory devices.
Innovation Solution
The use of asymmetric gate patterns within vertical stacks of nonvolatile memory cells, where the first and second gate patterns are separated by multi-layered dielectric patterns, including tunnel insulating layers, charge storage layers, barrier layers, and metal oxide layers, allows for reduced distance between gate patterns, enhancing integration density without the need for additional insulation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional symmetric gate patterns with uniform insulation layers are used, then manufacturing simplicity is maintained, but gate pattern separation distance cannot be reduced further, limiting integration density
Solution Approach 1:
The patent applies asymmetry by using different thicknesses for the first and second multi-layered dielectric patterns separating adjacent gate patterns. Specifically, the first dielectric pattern has a first thickness while the second dielectric pattern has a second thickness that is different from the first, allowing optimized spacing between gate patterns while maintaining electrical isolation. This asymmetric configuration enables reduced overall separation distance compared to uniform thickness designs, thereby increasing integration density without compromising manufacturing feasibility.
2Reliability
If additional insulation layers are added between gate patterns, then electrical isolation is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent implements multi-functionality by designing the multi-layered dielectric patterns to serve multiple purposes simultaneously. Each dielectric pattern includes a tunnel insulating layer, a charge storage layer, and a barrier layer, which collectively provide electrical isolation between gate patterns while also functioning as memory storage elements. This eliminates the need for separate dedicated insulation layers, reducing device complexity while maintaining reliable electrical isolation.
Solution Approach 2:
The patent merges the insulation function with the memory storage function by integrating the dielectric patterns that provide electrical isolation with the charge storage layers. The same multi-layered dielectric structures that isolate adjacent gate patterns electrically also serve as the memory cells for data storage, thereby combining multiple functions into a single structural element and avoiding additional insulation layers.
3Quantity of substance
If gate patterns are placed closer together, then integration density increases, but electrical interference and insulation challenges arise
Solution Approach 1:
The patent uses composite materials in the form of multi-layered dielectric patterns consisting of different material layers with complementary properties. The tunnel insulating layer provides electrical isolation, the charge storage layer offers high dielectric constant for charge retention, and the barrier layer prevents charge leakage. This composite structure enables effective electrical interference prevention even when gate patterns are placed at reduced distances, allowing higher integration density without compromising electrical performance.
Data Source
AI summary
Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.