Asymmetric Gate Spacer for Low Capacitance
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Solution Overview
Problem
Conventional techniques to combat the Miller effect, such as cascode configurations and thickened spacers, either consume additional area and power or result in an RC penalty, making them inefficient for reducing gate-drain overlap capacitance in transistors.
Innovation Solution
An asymmetric gate spacer configuration is implemented, where a second spacer is deposited inside the gate area and selectively retained on the drain side while removed on the source side, reducing gate-drain overlap capacitance without sacrificing area or power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If cascode configuration is used to combat the Miller effect, then gate-drain overlap capacitance is reduced and bandwidth is improved, but additional area and power are consumed
Solution Approach 1:
The patent applies asymmetry by implementing different spacer thicknesses on the source and drain sides of the gate. Specifically, a first spacer with a first thickness is formed on the source side, while a second spacer with a second thickness (greater than the first) is formed on the drain side. This asymmetric configuration selectively increases the drain-side spacer thickness to reduce gate-drain overlap capacitance without proportionally increasing overall device area, thereby resolving the contradiction between capacitance reduction and area consumption.
2Object-affected harmful factors
If uniform thickened spacers are used to reduce overlap capacitance, then gate-drain overlap capacitance is reduced, but RC penalty increases
Solution Approach 1:
The patent applies local quality by making the spacer thickness location-dependent rather than uniform. The drain-side spacer is thickened to specifically address the gate-drain overlap capacitance problem, while the source-side spacer maintains a smaller thickness. This localized thickening approach reduces the harmful capacitance effect where it occurs (at the drain side) without unnecessarily increasing resistance or creating RC penalties across the entire device structure.
3Object-affected harmful factors
If uniform thickened spacers are used to reduce overlap capacitance, then gate-drain overlap capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the spacer structure into distinct segments: a first spacer on the source side with a first thickness, and a second spacer on the drain side with a second thickness. This segmentation allows each spacer to be independently optimized for its specific function - the source-side spacer for basic isolation while the drain-side spacer for capacitance reduction - thereby achieving the desired capacitance reduction without requiring overly complex uniform thickening across the entire gate structure.
Data Source
AI summary
An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.