Asymmetric Gate Stack Layout for HEMT Current Collapse Suppression
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Solution Overview
Problem
High-power high electron mobility transistors (HEMTs) face issues such as gate leakage, time-dependent dielectric breakdown (TDDB), and current collapse when subjected to high voltages, leading to unsatisfactory performance in high-power components.
Innovation Solution
A semiconductor structure design with a gate structure featuring an extension portion near the drain side, incorporating specific doping concentrations and distances between semiconductor layers, forms an extended drain region to suppress current collapse and enhance device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure is designed with an extension portion near the drain side, then current collapse is suppressed and device reliability is improved, but the device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple components: a first gate electrode, a second gate electrode, and an extension portion. This segmentation allows each component to perform its function independently, with the extension portion specifically addressing current collapse near the drain region while the main gate electrodes control the channel, thus improving reliability without overwhelming complexity
Solution Approach 2:
The gate structure extends in the lateral dimension beyond the channel region, creating an extension portion that overlaps with the drain region. This dimensional extension allows the gate to influence the electric field distribution in the drain area, suppressing current collapse through field effect without requiring changes to the vertical stack structure
2Reliability
If the first distance is made larger to suppress current collapse, then device reliability improves, but the area occupied by the gate structure increases
Solution Approach 1:
The extension portion is localized specifically near the drain side where current collapse occurs, with the first distance optimized to be greater than the second distance. This local quality approach concentrates the reliability improvement function where it is most needed, rather than uniformly increasing gate dimensions across the entire device
Solution Approach 2:
The gate structure is designed asymmetrically with respect to the channel, having an extension portion that protrudes toward the drain region. This asymmetry creates unequal distances: the first distance from the extension portion to the drain is greater than the second distance to the source, allowing targeted suppression of drain-side current collapse with minimal area penalty
Data Source
AI summary
The disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a base pattern including a channel region and a drain region, a first semiconductor layer on the channel region of the base pattern, and a gate structure on the first semiconductor layer. The gate structure includes a first stack disposed on the first semiconductor layer and a second stack disposed on the first stack. The first stack includes a first sidewall adjacent to the drain region and a second sidewall opposite to the first sidewall in a first direction parallel to a top surface of the base pattern. The first sidewall is at a first distance from the second stack in the first direction, and the second sidewall is at a second distance from the second stack in the first direction. The first distance is greater than the second distance.