Asymmetric Gate Transistors for Continuous Overlay Error Measurement
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Solution Overview
Problem
Existing methods for measuring overlay errors in lithographic processes can only determine discrete values, lacking the precision needed for fine-grained measurements, which requires a large number of structures and measurements.
Innovation Solution
A semiconductor device comprising a first and second transistor with non-uniform gates, where the second gate is oriented to have an opposite effect of overlay errors on device parameters compared to the first transistor, allowing for continuous measurement of overlay errors by determining device parameter differences between the two transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If electrical measurements are applied on arrays of structures with various known displacements to determine overlay error, then overlay measurement can be performed, but the precision is limited to the built-in displacement and fine-grained measurement requires a large amount of structures and measurements
Solution Approach 1:
The patent changes the parameter of gate shape from uniform to non-uniform (asymmetric), where the gate width varies along the channel length. This parameter change enables continuous overlay error measurement through device parameter differences, eliminating the need for multiple discrete structures with various known displacements. The asymmetric gate configuration creates a direct relationship between overlay error and measurable device parameters, achieving fine-grained precision without increasing device complexity
Solution Approach 2:
The patent replaces the mechanical/discrete measurement system (arrays of structures with built-in displacements) with an electrical measurement system based on transistor device parameters. By measuring electrical characteristics of transistors with asymmetric gates, the system achieves continuous overlay error detection without requiring physical displacement structures, thereby reducing the amount of structures and measurements needed
2Measurement precision
If discrete values of overlay error are determined using prior art methods, then overlay measurement can be performed, but continuous measurement with higher precision is not achieved
Solution Approach 1:
The patent introduces asymmetric gate geometry as a key parameter change, where the gate width varies continuously along the channel length rather than being uniform. This parameter transformation enables the extraction of continuous overlay error values from device parameter measurements, providing the precision needed for fine-grained alignment control in manufacturing processes
Data Source
AI summary
A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction. The first and second gate each have a non-uniform shape, and the second gate is oriented with respect to an orientation of the first gate in such a way that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on the device parameter of the first transistor.