Asymmetric Gate Wiring for Semiconductor Devices
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Solution Overview
Problem
In semiconductor devices, the gate voltage fluctuates due to mutual inductances from source wires, causing instability, particularly when currents vary over time.
Innovation Solution
The semiconductor device design includes a gate wiring with a shorter first part opposing the first wiring and a longer second part opposing the second wiring, reducing mutual inductances and stabilizing the gate voltage. This configuration, combined with wide bandgap semiconductors allowing greater current flow and closer wiring patterns, further minimizes voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate wiring is made longer to connect to the semiconductor chip, then the electrical connection is improved, but the mutual inductance from source wires increases causing gate voltage fluctuation
Solution Approach 1:
The gate wiring is designed with non-uniform segment lengths where the first segment (opposing the first source wiring) has a different length than the second segment (opposing the second source wiring). This local variation in geometry optimizes the electromagnetic coupling characteristics to reduce mutual inductance effects while maintaining electrical connection reliability.
Solution Approach 2:
The gate wiring employs an asymmetric configuration where the first and second segments have different lengths relative to the source wirings. This asymmetry is deliberately introduced to balance and reduce the cumulative mutual inductance from multiple source wires, thereby stabilizing the gate voltage despite the necessarily long connection length.
2Area of stationary object
If the distance between gate wiring and source wirings is reduced to minimize area, then the device area is reduced, but the mutual inductance increases causing greater gate voltage fluctuation
Solution Approach 1:
The gate wiring segments are designed with different lengths to create localized electromagnetic coupling characteristics. By making the first segment shorter than the second segment, the design optimizes the trade-off between area efficiency and mutual inductance reduction, achieving compact layout while minimizing voltage fluctuation.
3Power
If multiple source wirings are used to increase current capacity, then the power handling capability is improved, but the cumulative mutual inductance increases causing greater gate voltage fluctuation
Solution Approach 1:
The gate wiring is divided into segments with different lengths corresponding to each source wiring connection. This segmentation allows differential optimization of electromagnetic coupling for each source wiring, reducing the cumulative mutual inductance effect while maintaining the high current capacity provided by multiple parallel source wirings.
Solution Approach 2:
The gate wiring is segmented into multiple sections, each with optimized length characteristics relative to the corresponding source wiring. This segmentation strategy enables independent optimization of electromagnetic coupling for each connection point, thereby reducing the overall cumulative mutual inductance while preserving the power handling capability of the multi-wiring configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively inhibits gate voltage fluctuations by optimizing wiring configurations and materials, ensuring stable operation even with varying currents, and uniformizing influences across adjacent semiconductor chips.
Implementation Method 1
When currents flowing through the first and second wirings vary with time, the gate wiring is susceptible to mutual inductances received from the first and second wirings because of the electromagnetic effect.
Data Source
AI summary
A semiconductor device includes at least one semiconductor chip, a gate wiring connected to the at least one semiconductor chip, a first wiring connected to the at least one semiconductor chip, and a second wiring connected to the at least one semiconductor chip. The first and second wirings extend along the gate wiring. The first wiring is arranged between the gate wiring and second wiring. The first wiring is the wiring closest to the gate wiring. A first part of the gate wiring opposing the first wiring is shorter than a second part of the gate wiring opposing the second wiring.