Asymmetric Multi-GPU Video Processing Pipeline

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Solution Overview

Problem

Current video processing systems face limitations in throughput due to the need for functionally identical GPUs, which restricts the number and complexity of processing procedures that can be executed on a single GPU, especially for high-definition video images, leading to potential frame dropping and poor video quality.

Innovation Solution

A system that divides video processing into separate tasks, where a first media processing device performs decoding and a second media processing device performs post-processing, allowing multiple frames to be processed simultaneously, even if the GPUs have different processing capabilities and memory sizes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple functionally identical GPUs are configured to work in parallel, then video processing throughput is increased, but the system loses flexibility and adaptability when adding or upgrading GPUs

Engineering Contradiction:
Improvevideo processing throughputVSAvoidGPU compatibility and upgrade flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The video processing pipeline is segmented into multiple independent processing stages (e.g., decode, post-processing, effects). Each GPU can be assigned to handle specific stages based on its capabilities, allowing heterogeneous GPUs to work together in parallel without requiring functional identity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system creates a universal processing framework where different GPU types can perform different functions within the same pipeline. The host system dynamically assigns tasks to available GPUs based on their capabilities, making the system adaptable to various GPU configurations and upgrades

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If more video processing procedures are applied to a single GPU, then video quality is improved, but processing time increases causing frame dropping

Engineering Contradiction:
Improvevideo qualityVSAvoidframe processing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Complex video processing procedures are divided into multiple independent processing stages that can be distributed across multiple GPUs. This parallelization maintains high video quality through multiple processing steps while reducing overall processing time by executing stages simultaneously on different GPUs

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from single-GPU sequential processing to multi-GPU parallel processing, adding a temporal dimension to the processing pipeline. Multiple frames can be processed at different stages simultaneously, increasing throughput and preventing frame dropping while maintaining quality

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If high definition video processing is performed, then image quality is improved, but processing complexity and time requirements increase

Engineering Contradiction:
Improveimage qualityVSAvoidprocessing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

High definition video processing is segmented into distinct processing stages (decode, post-processing, effects, output). Each stage can be optimized independently and distributed to appropriate GPUs, managing complexity while maintaining high image quality through specialized processing at each stage

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7768517B2Asymmetric multi-GPU processing
Publication Date: 2010.08.03 NVIDIA CORP
  • US7768517B2 patent drawing
  • US7768517B2 patent drawing
  • US7768517B2 patent drawing

AI summary

A system for processing video data includes a host processor, a first media processing device coupled to a first buffer, the first media processing device configured to perform a first processing task on a frame of video data, and a second media processing device coupled to a second buffer, the second media processing device configured to perform a second processing task on the processed frame of video data. The architecture allows the two devices to have asymmetric video processing capabilities. Thus, the first device may advantageously perform a first task, such as decoding, while the second device performs a second task, such as post processing, according to the respective capabilities of each device, thereby increasing processing efficiency relative to prior art systems. Further, one driver may be used for both devices, enabling applications to take advantage of the system's accelerated processing capabilities without requiring code changes.