Asymmetric Image Splitter Clocking Without Per-Display PLLs
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Solution Overview
Problem
Current GMSL serializer and deserializer systems require phase lock loop (PLL) oscillators to generate video clocks for individual displays, which increases power consumption, size, and cost, especially as the number of displays increases in vehicles.
Innovation Solution
Implementing an asymmetric image splitter clock generation block using a fractional clock divider circuit with a one-bit sigma-delta modulator and digital proportional error feedback control loop, eliminating the need for PLLs and allowing for the generation of compatible display clock frequencies for multiple displays from a single super-frame image stream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL oscillators are used to generate video clocks for individual displays, then reliable clock generation is achieved, but power consumption increases and cost increases
Solution Approach 1:
The patent combines multiple clock generation functions into a single fractional-N PLL oscillator. Instead of using separate PLLs for each display, the system uses one PLL that can dynamically generate different clock frequencies for multiple displays through fractional division ratios, thereby reducing power consumption while maintaining reliable clock generation.
Solution Approach 2:
The fractional-N PLL oscillator is designed to perform multiple functions: it can generate clock signals for different displays with different resolutions and refresh rates using a single device. The oscillator adapts its division ratio dynamically to serve multiple display configurations, eliminating the need for dedicated PLLs for each display type.
2Reliability
If PLL oscillators are used to generate video clocks for individual displays, then reliable clock generation is achieved, but device size increases and cost increases
Solution Approach 1:
The patent merges multiple clock generation circuits into a single fractional-N PLL oscillator. This consolidation reduces the overall device size and complexity by eliminating redundant PLL components while maintaining the ability to provide reliable clock signals to multiple displays with different requirements.
3Adaptability or versatility
If multiple PLL oscillators are used to support multiple displays with different resolutions, then display compatibility is improved, but power consumption increases
Solution Approach 1:
The patent implements a dynamic fractional-N PLL oscillator that can change its division ratio in real-time based on the display requirements. This dynamic adjustment allows a single oscillator to adapt to different display resolutions and refresh rates, providing high display compatibility without the power consumption penalty of multiple static PLLs.
Solution Approach 2:
The system changes the operational parameters of the PLL oscillator, specifically the division ratio, to match different display requirements. By dynamically adjusting the division ratio parameter, the single oscillator can generate appropriate clock frequencies for various display configurations, achieving versatility without multiplying the number of oscillators.
4Adaptability or versatility
If PLL oscillators are used for each display, then individualized clock generation is achieved, but cost increases
Solution Approach 1:
The patent combines the functionality of multiple individualized clock generators into a single fractional-N PLL oscillator. This consolidation reduces system cost by eliminating redundant components while maintaining the ability to provide customized clock signals to each display through dynamic parameter adjustment.
Data Source
AI summary
Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.